Question

我试图在verilog中进行仲裁。但我收到错误："endmodule"

这是我的代码：

module rr_arbiter (
clk, // positive edge trigger
reset,  // negative edge trigger
req,grant,
priority, priority_req);

input clk, reset;
input [3:0]req;
input priority;
input [1:0] priority_req;

output [3:0] grant; 
integer i;
always@(posedge clk) begin

if (reset) begin
//all grant = 0
for(i=0;i<4;i=i+1)
grant[i] = 0; //reset
end

else
if(priority == 0)begin
//0,1,2,3,0,1,2,3 ....
for(i=0;i<4;i=i+1)
if(req[i] == 0)
grant[0] <= req[i];
else if(req[i] == 1)
grant[1] <= req[i];
else if(req[i] == 2)
grant[2] <= req[i];
else if(req[i] == 3)
grant[3] <= req[i];
end

if(priority == 1)begin
if (reset) begin
//all grant = 0
for(i=0;i<4;i=i+1)
grant[i] = 0; //reset
end

if(priority_req==0)begin //0
//counter : 0 0 1 2 3 0 0 1 2 3 ..
for(i=0;i<4;i=i+1)
if(req[i] == 0)
grant[0] <= req[i];
grant[1] <= req[i];
if(req[i] == 1)
grant[2] <= req[i];
if(req[i] == 2)
grant[3] <= req[i];
if(req[i] == 3)
grant[0] <= req[i];
end

else if(priority_req==1)begin
//counter : 0 1 1 2 3 0 1 1 2 3 ..
for(i=0;i<4;i=i+1)
if(req[i] == 0)
grant[0] <= req[i];
if(req[i] == 1)
grant[1] <= req[i];
grant[2] <= req[i];
if(req[i] == 2)
grant[3] <= req[i];
if(req[i] == 3)
grant[0] <= req[i];
end
else if(priority_req==2)begin
//counter : 0 1 2 2 3 0 1 2 2 3 ..
for(i=0;i<4;i=i+1)
if(req[i] == 0)
grant[0] <= req[i];
if(req[i] == 1)
grant[1] <= req[i];
if(req[i] == 2)
grant[2] <= req[i];
grant[3] <= req[i];
if(req[i] == 3)
grant[0] <= req[i];
end

else if(priority_req==3)begin
//counter : 0 1 2 3 3 0 1 2 3 3 ..
for(i=0;i<4;i=i+1)
if(req[i] == 0)
grant[0] <= req[i];
if(req[i] == 1)
grant[1] <= req[i];
if(req[i] == 2)
grant[2] <= req[i];
if(req[i] == 3)
grant[3] <= req[i];
grant[0] <= req[i];
end

else if(priority_req>3)begin
for(i=0;i<4;i=i+1)
grant[i] = 0;
end
end  

endmodule

我想制作循环优先仲裁模块。

我不确定我是否写了错误的一端。我担心问题是如果报价有问题或是否应该从头开始重新编码。

Answer 1

Verilog代码中的许多语法错误指向问题后面的行。任何具有Verilog模式的编辑器进行正确的代码缩进操作都会显示您在end之前错过了endmodule。

其他错误：需要将grant定义为reg。你也有很多req[i] == 3的代码。但是req [i]是一个单一的位。考虑查看casez语句。

我在modelsim“endmodule”中的verilog中出错

1 个答案: