如何使用定义为逻辑的术语创建位范围

时间:2017-11-10 15:38:33

标签: verilog system-verilog

我理解下面的代码不会编译,但是有类似的东西编译吗?

logic [7:0] complete_set, partial_set;  
logic [2:0] msb_bit, lsb_bit;  

always_comb complete_set = <driven by a logic equation>;  
always_comb msb_bit = <driven by a logic equation>;  
always_comb lsb_bit = <driven by a logic equation>;  

always_comb partial_set[msb_bit:lsb_bit] = complete_set[msb_bit:lsb_bit];

2 个答案:

答案 0 :(得分:0)

你可以像这样做一些按位的决定。我只是假设您想将其他位设置为零,但您也可以将其设置为不关心(1&#39; bx)。

for(i = 0; i < 8; i = i + 1) begin
    partial_set[i] = (i < lsb_bit) || (i > msb_bit) ? 1'b0 : complete_set[i];
end

答案 1 :(得分:0)

假设您希望未指定的位为0,则可以在一行中执行此操作:

   always_comb partial_set = complete_set & (2**(msb_bit+1-lsb_bit)-1)<<lsb_bit;

但我认为for循环对其他人来说更容易理解

always_comb begin
       partial_set = '0; // or whatever the unspecified bits should be
       for(int ii = lsb_bit; ii <= msb_bit; ii++)
           partial_set[ii] = complete_set[ii]
    end