Question

在Zynq Ultrascale +（电路板ZCU102 rev 1）上引导基于Linux的操作系统，并按here中所述配置内核，具有由Vivado SDK 2017.2自动生成的设备树，如下所示：

    gem0: ethernet@ff0b0000 {
        compatible = "cdns,zynqmp-gem";
        status = "disabled";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x39 0x4 0x0 0x39 0x4>;
        reg = <0x0 0xff0b0000 0x0 0x1000>;
        clock-names = "pclk", "tx_clk", "hclk";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0x8 0x874>;
        power-domains = <0xd>;
        clocks = <0x3 0x2d 0x3 0x2d 0x3 0x31>;
    };

    gem1: ethernet@ff0c0000 {
        compatible = "cdns,zynqmp-gem";
        status = "disabled";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x3b 0x4 0x0 0x3b 0x4>;
        reg = <0x0 0xff0c0000 0x0 0x1000>;
        clock-names = "pclk", "tx_clk", "hclk";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0x8 0x875>;
        power-domains = <0xe>;
        clocks = <0x3 0x2e 0x3 0x2e 0x3 0x32>;
    };

    gem2: ethernet@ff0d0000 {
        compatible = "cdns,zynqmp-gem";
        status = "disabled";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x3d 0x4 0x0 0x3d 0x4>;
        reg = <0x0 0xff0d0000 0x0 0x1000>;
        clock-names = "pclk", "tx_clk", "hclk";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0x8 0x876>;
        power-domains = <0xf>;
        clocks = <0x3 0x2f 0x3 0x2f 0x3 0x33>;
    };

    gem3: ethernet@ff0e0000 {
        compatible = "cdns,zynqmp-gem";
        status = "okay";
        interrupt-parent = <0x4>;
        interrupts = <0x0 0x3f 0x4 0x0 0x3f 0x4>;
        reg = <0x0 0xff0e0000 0x0 0x1000>;
        clock-names = "pclk", "hclk", "tx_clk", "rx_clk";
        #address-cells = <0x1>;
        #size-cells = <0x0>;
        #stream-id-cells = <0x1>;
        iommus = <0x8 0x877>;
        power-domains = <0x10>;
        clocks = <0x3 0x1f 0x3 0x34 0x3 0x30 0x3 0x34>;
        phy-mode = "rgmii-id";
        xlnx,ptp-enet-clock = <0x0>;
    };

启动时，其中一条内核消息是：

macb ff0e0000.ethernet eth0: Could not attach to PHY

，如果你执行：

ifconfig -a

shell提示：

root@linaro-developer:~# ifconfig -a
can0: flags=128<NOARP>  mtu 16
        unspec 00-00-00-00-00-00-00-00-00-00-00-00-00-00-00-00  txqueuelen 10  (UNSPEC)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0
        device interrupt 11  

lo: flags=73<UP,LOOPBACK,RUNNING>  mtu 65536
        inet 127.0.0.1  netmask 255.0.0.0
        inet6 ::1  prefixlen 128  scopeid 0x10<host>
        loop  txqueuelen 1  (Local Loopback)
        RX packets 6  bytes 372 (372.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 6  bytes 372 (372.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

sit0: flags=128<NOARP>  mtu 1480
        sit  txqueuelen 1  (IPv6-in-IPv4)
        RX packets 0  bytes 0 (0.0 B)
        RX errors 0  dropped 0  overruns 0  frame 0
        TX packets 0  bytes 0 (0.0 B)
        TX errors 0  dropped 0 overruns 0  carrier 0  collisions 0

没有eth。关于如何解决这个问题的建议？

Answer 1

解决方案：

有必要在system-top.dts中添加（由Vivado自动生成）文件＆＃34; zcu102-revb.dtsi＆＃34;这样：

/*
 * CAUTION: This file is automatically generated by Xilinx.
 * Version:  
 * Today is: Wed Sep 13 12:25:12 2017
*/


/dts-v1/;
/include/ "zynqmp.dtsi"
/include/ "zynqmp-clk-ccf.dtsi"
/include/ "zcu102-revb.dtsi"
/include/ "pl.dtsi"
/include/ "pcw.dtsi"

....etc....

请注意，该文件可以在＆＃34; xilinx-zcu102-zu9-es2-rev1.0-2017.2＆＃34;包（找到它here, in the Xilinx webpage）。

也可以在文件夹＆＃34; linux-xlnx / arch / arm64 / boot / dts / xilinx /＆＃34;中的内核linux源文件中找到它。

生成新设备树后，可以使用eth0和内核提示：

macb ff0e0000.ethernet eth0: Cadence GEM rev 0x50070106 at 0xff0e0000 irq 31 (00:0a:35:03:77:52)

此外，我刚刚在Xilinx forum中发布了答案。

macb ff0e0000.ethernet eth0：无法连接到PHY

1 个答案: