Question

我正在尝试使用EDA Playground学习Verilog。我试图通过组合下一个状态和输出逻辑来重写此处示例中的Moore Machine：http://www.edaplayground.com/x/B。

这就是我所做的：

    /*
 * Finite state machine.Moore Machine
 * If input 'a' is asserted, the state machine
 * moves IDLE->STATE_1->FINAL and remains in FINAL.
 * If 'a' is not asserted, FSM returns to idle.
 * Output 'out1' asserts when state machine is in
 * STATE_1. 'out2' asserts when state machine is in
 * FINAL state.
 */ 
module fsm(clk, reset, a, out1, out2);
  input  clk;
  input  a;
  input reset;
  output out1, out2;
  // State encodings
  parameter [2:0]
    IDLE    = 3'b001,
    STATE_1 = 3'b010,
    FINAL   = 3'b100;  
  reg [2:0] /* synopsys enum states */ current_state, next_state;
// synopsys state_vector current_state
reg out1, out2;
  /*------- Sequential Logic ----*/
always@(posedge clk or negedge reset)
  if (!reset) current_state <= IDLE;
    else current_state <= next_state;
/* next state logic and output logic – combined so as to share state decode logic */
  always @(posedge clk or negedge reset) 
    begin
      out1 = 0; out2 = 0;
      case (current_state)
        IDLE:
          begin
            if (a) 
              begin out1= 1; out2=0; next_state <= STATE_1; end  
            else  
              begin out1= 0; out2=0;next_state <= IDLE;      end 
          end
        STATE_1:
          begin
            if (a) 
              begin out1= 0; out2=1;next_state <= FINAL;    end
            else 
               begin out1= 0; out2=0;next_state <= IDLE; end
          end
        FINAL:
          begin
            if (a) 
             begin out1= 0; out2=1;next_state <= FINAL; end 
            else 
              begin  out1= 0; out2=0;next_state <= IDLE;end
          end
        default:
          begin out1= 0; out2=0; next_state <= IDLE;end
      endcase
    end

endmodule

然而，结果不正确，我得到了

# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
# KERNEL: Initial a: 0,out1: x, out2: x
# KERNEL: IDLE a: 0 ,out1: 0, out2: 0
# KERNEL: STATE_1 a: 1 ,out1: 1, out2: 0
# KERNEL: FINAL a: 1 ,out1: 1, out2: 0
# KERNEL: FINAL a: 1,out1: 1, out2: 0
# KERNEL: IDLE a: 0 ,out1: 0, out2: 0
# KERNEL: Simulation has finished. There are no more test vectors to simulate.
exit

但是，预期结果应为：

run -all;
# KERNEL: Initial a: 0,out1: x, out2: x
# KERNEL: IDLE a: 0 ,out1: 0, out2: 0
# KERNEL: STATE_1 a: 1 ,out1: 1, out2: 0
# KERNEL: FINAL a: 1 ,out1: 0, out2: 1
# KERNEL: FINAL a: 1,out1: 0, out2: 1
# KERNEL: IDLE a: 0 ,out1: 0, out2: 0
# KERNEL: Simulation has finished. There are no more test vectors to simulate.

我做错了什么？

这是测试夹具：

// Testbench
module test;

  reg  clk, reset, a;
  wire out1, out2;

  // Instantiate device under test
  fsm FSM(.clk(clk),.reset(reset),
          .a(a),
          .out1(out1),
          .out2(out2));

  initial begin
    // Dump waves
    $dumpfile("dump.vcd");
    $dumpvars(1, test);

    clk = 0;
    reset = 1;
    a = 0;
    $display("Initial a: %0h,out1: %0h, out2: %0h",
      a,out1, out2);

    toggle_clk;
    $display("IDLE a: %0h ,out1: %0h, out2: %0h",
     a, out1, out2);

    a = 1;
    toggle_clk;
    $display("STATE_1 a: %0h ,out1: %0h, out2: %0h",
      a,out1, out2);

    toggle_clk;
    $display("FINAL a: %0h ,out1: %0h, out2: %0h",
      a,out1, out2);

    toggle_clk;
    $display("FINAL a: %0h,out1: %0h, out2: %0h",
      a,out1, out2);

    a = 0;
    toggle_clk;
    $display("IDLE a: %0h ,out1: %0h, out2: %0h",
      a,out1, out2);
  end

  task toggle_clk;
    begin
      #10 clk = ~clk;
      #10 clk = ~clk;
    end
  endtask

endmodule

非常感谢您提前，

CS

Answer 1

我试图在Verilog 95中实现Mealy机器，但是，我的sesetivity列表不完整。非常感谢格雷格的帮助。

   /*
 * Finite state machine.Moore Machine
 * If input 'a' is asserted, the state machine
 * moves IDLE->STATE_1->FINAL and remains in FINAL.
 * If 'a' is not asserted, FSM returns to idle.
 * Output 'out1' asserts when state machine is in
 * STATE_1. 'out2' asserts when state machine is in
 * FINAL state.
 */ 
module fsm(clk, reset, a, out1, out2);
  input  clk;
  input  a;
  input reset;
  output out1, out2;
  // State encodings
  parameter [2:0]
    IDLE    = 3'b001,
    STATE_1 = 3'b010,
    FINAL   = 3'b100;  
  reg [2:0] /* synopsys enum states */ current_state, next_state;
// synopsys state_vector current_state
reg out1, out2;
  /*------- Sequential Logic ----*/
always@(posedge clk or negedge reset)
  if (!reset) current_state <= IDLE;
    else current_state <= next_state;
/* next state logic and output logic – combined so as to share state decode logic */
  always @(posedge clk or negedge reset or a) 
    begin
      out1 = 0; out2 = 0;
      case (current_state)
        IDLE:
          begin
            if (a) 
              begin out1= 1; out2=0; next_state = STATE_1; end  
            else  
              begin out1= 0; out2=0;next_state = IDLE;      end 
          end
        STATE_1:
          begin
            if (a) 
              begin out1= 0; out2=1;next_state = FINAL;    end
            else 
               begin out1= 0; out2=0;next_state = IDLE; end
          end
        FINAL:
          begin
            if (a) 
             begin out1= 0; out2=1;next_state = FINAL; end 
            else 
              begin  out1= 0; out2=0;next_state = IDLE;end
          end
        default:
          begin out1= 0; out2=0; next_state = IDLE;end
      endcase
    end

endmodule

一个非常简单的FSM的奇怪行为

1 个答案: