我是verilog编码的新手,我试图为停车系统编写verilog代码。以下是我的代码。每当sense_entry变高时,我想分配一个停放槽。在Altera板中,当sense_entry变为1时,所有的槽都被分配。我才知道它是逻辑综合错误。怎么解决这个? 示例:当sense_entry第一次变为1时,应分配slota。应该分配第二次插槽。
`module ParkingSystem(clock,reset,sense_entry,sense_exit_A,sense_exit_B,sense_exit_C,sense_exit_D,
slota,slotb,slotc,slotd);
input sense_entry,sense_exit_A,sense_exit_B,sense_exit_C,sense_exit_D,clock,reset;
output slota,slotb,slotc,slotd;
reg slota,slotb,slotc,slotd;
initial
begin
slota=1'b1;
slotb=1'b1;
slotc=1'b1;
slotd=1'b1;
end
always@(reset or sense_entry or sense_exit_A or sense_exit_B or sense_exit_C or sense_exit_D)
begin
if(reset==1'b1)
begin
slota=1'b1;
slotb=1'b1;
slotc=1'b1;
slotd=1'b1;
$display("Reset Pressed");
$display("slot A is alloted");
$display("slot B is alloted");
$display("slot C is alloted");
$display("slot D is alloted");
end
else if(sense_entry==1'b1)
begin
if(slota==1'b1)
begin
slota=1'b0;
$display("slot A is alloted");
end
else if(slotb==1'b1)
begin
slotb=1'b0;
$display("slot B is alloted");
end
else if(slotc==1'b1)
begin
slotc=1'b0;
$display("slot C is alloted");
end
else if(slotd==1'b1)
begin
slotd=1'b0;
$display("slot D is alloted");
end
else
$display("slots are full");
end
else if(sense_exit_A==1'b1)
begin
if(slota==1'b0)
begin
slota=1'b1;
$display("slot A is dealloted");
end
else
$display("No Car in slot A");
end
else if(sense_exit_B==1'b1)
begin
if(slotb==1'b0)
begin
slotb=1'b1;
$display("slot B is dealloted");
end
else
$display("No Car in slot B");
end
else if(sense_exit_C==1'b1)
begin
if(slotc==1'b0)
begin
slotc=1'b1;
$display("slot C is dealloted");
end
else
$display("No Car in slot C");
end
else if(sense_exit_D==1'b1)
begin
if(slotd==1'b0)
begin
slotd=1'b1;
$display("slot D is dealloted");
end
else
$display("No Car in slot D");
end
end
endmodule
`