Question

我在systemverilog中有这个代码，我必须在for循环中使用十六进制数字。我正在尝试下面的语法和代码。

genvar i,j;

localparam int i_d = 1;

localparam int j_d = 134;

generate

for (i = 8'h01; i <= MAX1; i = i + INCR)

begin

    add_bit[i_d] = (creg_add == i);

    i_d = i_d + 1;

end

for (j = 8'h86; j <= MAX2; j = j + INCR)

begin

    add_bit[j_d] = (creg_add == j);

    j_d = j_d + 1;

end

endgenerate

但我正面临这个错误。有人可以帮助我吗？

Error-[SE] Syntax error
 Following verilog source has syntax error :
  "creg.vs",
  715: token is '['
              add_bit[i_d] = (creg_add == i);
              ^

Answer 1

在精化时（预模拟）评估

generate块。您可以在其中包含always块，assign语句，模块实例和本地范围的变量deescalation。不允许直接分配将在always块或assign语句之外不断更新的值。

localparam是常量，因此行i_d = i_d + 1是非法的。

更简单的解决方案是在组合总是阻止中使用程序分配。

int i,j;
int i_d, j_d;
logic [WIDTH:0] add_bit;

always_comb begin
  i_d = 1;
  j_d = 134;
  add_bit = '0; // fill zeros in case of gap between last i_d and first j_d
  for (i = 8'h01; i <= MAX1; i = i + INCR)
  begin
    add_bit[i_d] = (creg_add == i);
    i_d = i_d + 1;
  end
  for (j = 8'h86; j <= MAX2; j = j + INCR)
  begin
    add_bit[j_d] = (creg_add == j);
    j_d = j_d + 1;
  end
end

Answer 2

这应该可以解决问题。

genvar i,j;

localparam int i_d = 1;

localparam int j_d = 134;

generate

for (i = 8'h01; i <= MAX1; i = i + INCR)

begin

    assign add_bit[i_d] = (creg_add == i);

    i_d = i_d + 1;

end

for (j = 8'h86; j <= MAX2; j = j + INCR)

begin

    assign add_bit[j_d] = (creg_add == j);

    j_d = j_d + 1;

end

endgenerate

verilog中的十六进制值为循环生成

2 个答案: