Question

~~我想让一些端口保持未连接状态，但所有未连接的端口都连接到GEN寄存器，如：~~

<击>
wire instance1_io_somePort; reg _GEN_3; // Want disable generation of this my_module instance1( ... .some_port(instance1_io_somePort) ) assign instance1_io__somePort = _GEN_3; // and this strings.

~~在chisel3中是否可以禁用对_GEN_X寄存器的任何赋值？~~

===== update_14_07_17 =====

关于io端口的问题，关于内部 GEN 信号的问题以下示例

import chisel3._

class A extends Bundle {
  val in = Input(Bool())
  val out = Output(Bool())
}

class X extends Module {
  val io = IO(new Bundle {
    val A_IF = new A
  })
  val reg = RegInit(UInt(2.W), init = 0.U)


  io.A_IF.out := (reg === 2.U)

  when(io.A_IF.in === true.B){
    reg := 1.U
  }.elsewhen(io.A_IF.in === false.B){
    reg := 2.U
  }
}

object example extends App {
  Driver.execute(Array("-td", "./"), () => new X())
}

这个凿子代码生成一堆verilog

module X(
  input   clock,
  input   reset,
  input   io_A_IF_in,
  output  io_A_IF_out
);
  reg [1:0] reg$;
  reg [31:0] _GEN_2; // don't wanna this reg to appear
  wire  _T_7;
  wire [1:0] _GEN_0; // and this 
  wire  _T_12;
  wire  _T_15;
  wire [1:0] _GEN_1; // and this wires 
  assign io_A_IF_out = _T_7;
  assign _T_7 = reg$ == 2'h2;
  assign _GEN_0 = io_A_IF_in ? 2'h1 : reg$;
  assign _T_12 = io_A_IF_in == 1'h0;
  assign _T_15 = _T_12 & _T_12;
  assign _GEN_1 = _T_15 ? 2'h2 : _GEN_0;
`ifdef RANDOMIZE
  //chisels randomize code here
`endif
  always @(posedge clock) begin
    if (reset) begin
      reg$ <= 2'h0;
    end else begin
      if (_T_15) begin
        reg$ <= 2'h2;
      end else begin
        if (io_A_IF_in) begin
          reg$ <= 2'h1;
        end
      end
    end
  end
endmodule

我想知道，是否可以禁用_GEN_2和_GEN_1电线以及_GEN_0 reg的生成？为什么会出现这个一族？

Answer 1

_GEN 是由Firrtl生成的中间节点的前缀，它是Chisel3的IR和编译器。

这些中间节点是必需的，因为Firrtl每行只能发出一个Verilog操作。这种限制是由于Verilog通常很棘手的宽度语义 - 完全避免这些微妙的问题要安全得多。

Chisel3禁用GEN线

1 个答案: