ZYNQ7处理系统FCLK_CLK0和M_AXI_GPO_ACLK值为'X' - 强制未知

时间:2017-07-06 08:57:40

标签: vhdl xilinx vivado zynq xilinx-edk

我设计了一个用于数据传输的RGMII接口,并且第一步想要运行它来执行环回。

我已将Zynq7处理系统连接到此设计,以便通过FCLK_CLK0输出端口提供时钟信号。

尽管波形窗口成功打开,但运行行为模拟不会显示任何信号

运行后综合功能仿真并运行后实现功能仿真显示相同的波形输出,其中FCLK_CLK0和M_AXI_GP0_ACLK的值为'X'。

我已经尝试生成比特流,导出硬件并启动SDK以初始化PS。问题似乎仍然存在。

欢迎所有建议,非常感谢您寻求帮助

The link to schematic view is provided here

The link to functional simulation view is provided here

编辑:测试平台只是声明并实例化整个设计(包括PS和RGMII),否则无需执行任何操作。以下是测试平台:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL; 


USE ieee.numeric_std.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library std;
use std.textio.all;


entity TOP_WRAPPER_tb is
--  Port ( );
end TOP_WRAPPER_tb;

architecture Behavioral of TOP_WRAPPER_tb is
component TOP_WRAPPER is
  Port (    POE_CONFIG          :    out std_logic;
            POE_RST             :    out std_logic;
            POE_RX_D            :    in std_logic_vector (3 downto 0);
            POE_RX_CTL          :    in std_logic;
            POE_RX_CLK          :    in std_logic;

        POE_TX_CLK          :    out std_logic;

        POE_TX_D            :    out std_logic_vector (3 downto 0);
        POE_TX_CTL          :    out std_logic
        );
end component TOP_WRAPPER;



   signal  POE_CONFIG          :     std_logic;
   signal POE_RST              :     std_logic;
  signal  POE_RX_CTL           :    std_logic := '0';
   signal POE_RX_D             :    std_logic_vector (3 downto 0) := "0111";
  signal  POE_RX_CLK           :    std_logic:= '0';
   signal POE_TX_CLK           :     std_logic;
  signal  POE_TX_D             :     std_logic_vector (3 downto 0);
  signal  POE_TX_CTL           :     std_logic;
  signal iClkCount : integer range 0 to 10 := 0;

  --constant clock_25_period    : time := 40 ns;
 -- constant clock_2_5_period   : time := 400 ns;
 -- constant rgmii_rx_setup     : time := 2 ns;
 -- constant rgmii_rx_hold      : time := 0 ns;
 -- constant rgmii_tx_setup     : time := 2.5 ns;

constant clock_25_period    : time := 10 ns;
begin


  clock_25_process : process
 begin
    -------------------------non synthesizable tb-----------
     POE_RX_CLK <= not POE_RX_CLK;
     POE_RX_CTL <= not POE_RX_CTL;
     wait for clock_25_period / 2;
    ---------------------------------------------------------
   -- if(iClkCount = 10 ) then 
   --       POE_RX_CLK <= not POE_RX_CLK;
   --       POE_RX_CTL <= not POE_RX_CTL;
   --  else
   --      iClkCount <= iClkCount + 1;
   --  end if;

 end process;

UUT: TOP_WRAPPER 
  Port map (    POE_CONFIG => POE_CONFIG,
        POE_RST     => POE_RST,
        POE_RX_D    => POE_RX_D, 
        POE_RX_CTL  => POE_RX_CTL,  
        POE_RX_CLK   => POE_RX_CLK,    
        --Phy_en                    :    in std_logic;

        POE_TX_CLK  => POE_TX_CLK, 

        POE_TX_D  => POE_TX_D,
        POE_TX_CTL  => POE_TX_CTL 
        );


end Behavioral;

0 个答案:

没有答案