Question

来自代码主要来自myhdl的样本：

from myhdl import Signal, intbv, delay, always, now, Simulation, toVerilog

__debug = True

def ClkDriver(clk):
    halfPeriod = delay(10)
    @always(halfPeriod)
    def driveClk():
        clk.next = not clk
    return driveClk

def HelloWorld(clk, outs):

    counts = intbv(3)[32:]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts >= 3 - 1:
            counts.next = 0
        else:
            counts.next = counts + 1
        if __debug__:
            print "%s Hello World! outs %s %s" % (
              now(), str(outs), str(outs.next))

    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)

我希望它生成一个包含initial块的verilog程序，如：

module HelloWorld(...)
reg [31:0] counts;
initial begin
    counts = 32'h3
end
always @(...

如何生成initial块？

请注意，在old.myhdl.org/doku.php/dev:initial_values的google缓存中，它会链接到示例https://bitbucket.org/cfelton/examples/src/tip/ramrom/。所以看起来该功能应该得到支持。然而，rom示例生成静态case语句。那不是我想要的。

Answer 1

解决它的三个步骤：

更新到master上的最新myhdl或包含添加了问题87784ad或#105功能的哈希#150的版本。作为virtualenv的示例，运行git clone，然后运行pip install -e <path-to-myhdl-dir>。
将信号更改为列表。
在致电toVerilog.initial_values=True之前设置toVerilog。

以下是代码段。

def HelloWorld(clk, outs):

    counts = [Signal(intbv(3)[32:])]

    @always(clk.posedge)
    def sayHello():
        outs.next = not outs
        if counts[0] >= 3 - 1:
            counts[0].next = 0
        else:
            counts[0].next = counts[0] + 1
        if __debug__:
            print "%s Hello World! outs %s %s %d" % (
                  now(), str(outs), str(outs.next), counts[0])
    return sayHello

clk = Signal(bool(0))
outs = Signal(intbv(0)[1:])
clkdriver_inst = ClkDriver(clk)
toVerilog.initial_values=True
hello_inst = toVerilog(HelloWorld, clk, outs)
sim = Simulation(clkdriver_inst, hello_inst)
sim.run(150)

python myhdl包如何生成verilog初始块

1 个答案: