Question

I want to instanciate two DUT (Device under test) in the same verilog testbench and compare their output signals.

Actually the two devices will have the same inputs but diffrent outputs.

Any help please?

Answer 1

你需要创建一个顶层模块，它将封装dut和testbench。我想在测试平台下你的意思是你的df模型。您还需要创建一个测试平台模块，该模块将提供激励并以某种方式比较结果行为。

module top();
    // declare all your inputs needed to instantiate both models and tb
    // i.e.
    logic clk, in, out_dut, out_bfm;
    // instantiate your dut
    dut dut(clk, in, out_dut);

    // instantiate your bfm
    bfm bfm(clk, in , out_bfm);

    // instantiate your test bench module
    tb tb(clk, in, out_dut, out_bfm);

endmodule

tb将提供＆＃39; in＆＃39;两者兼而有之来自两者。您可以在测试平台中比较结果。

是的，您还必须生成所需的所有时钟。

当然，这只是必须完成的顶级架构。您需要查阅编码方法指南，了解如何组织它并编写测试台和测试台。

Instanciate the same device under test twice

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