Question

我有一个模块（称之为child），它声明了它的输入并输出为二维数组。我还有一个实例化parent的模块（child）。 2D阵列在parent中被分解为单个信号。

为了使parent和child之间的输入和输出正确分配，我必须反转输入和输出之间的连接顺序。

请参阅以下代码示例，以便更清楚地了解我的意思：

module child (
    // Inputs and outputs declared as 2D arrays
    input  [4:0] my_input[8],
    output [4:0] my_output[8]
    );

    // Dummy assignemts just for clarity, values will be printed in parent
    assign my_output[0] = 9;
    assign my_output[1] = 10;
    assign my_output[2] = 11;
    assign my_output[3] = 12;
    assign my_output[4] = 13;
    assign my_output[5] = 14;
    assign my_output[6] = 15;
    assign my_output[7] = 16;


    initial begin 
        #2;

        // Print out to show how inputs are driven by parent
        $display("in child, my_input[0]: %0d, expecting 1 (set by parent)", my_input[0]);
        $display("in child, my_input[1]: %0d, expecting 2 (set by parent)", my_input[1]);
        $display("in child, my_input[2]: %0d, expecting 3 (set by parent)", my_input[2]);
        $display("in child, my_input[3]: %0d, expecting 4 (set by parent)", my_input[3]);
        $display("in child, my_input[4]: %0d, expecting 5 (set by parent)", my_input[4]);
        $display("in child, my_input[5]: %0d, expecting 6 (set by parent)", my_input[5]);
        $display("in child, my_input[6]: %0d, expecting 7 (set by parent)", my_input[6]);
        $display("in child, my_input[7]: %0d, expecting 8 (set by parent)", my_input[7]);
    end
endmodule

module parent ();
    logic [4:0] the_input0;
    logic [4:0] the_input1;
    logic [4:0] the_input2;
    logic [4:0] the_input3;
    logic [4:0] the_input4;
    logic [4:0] the_input5;
    logic [4:0] the_input6;
    logic [4:0] the_input7;

    logic [4:0] the_output0;
    logic [4:0] the_output1;
    logic [4:0] the_output2;
    logic [4:0] the_output3;
    logic [4:0] the_output4;
    logic [4:0] the_output5;
    logic [4:0] the_output6;
    logic [4:0] the_output7;

    // Dummy assignemts just for clarity, values will be printed in child
    assign the_input0 = 1;
    assign the_input1 = 2;
    assign the_input2 = 3;
    assign the_input3 = 4;
    assign the_input4 = 5;
    assign the_input5 = 6;
    assign the_input6 = 7;
    assign the_input7 = 8;

    initial begin 
        #1;

        // Print out to show how inputs are driven by child
        $display("in parent, the_output0: %0d, expect 9 (set by child)", the_output0);
        $display("in parent, the_output1: %0d, expect 10 (set by child)", the_output1);
        $display("in parent, the_output2: %0d, expect 11 (set by child)", the_output2);
        $display("in parent, the_output3: %0d, expect 12 (set by child)", the_output3);
        $display("in parent, the_output4: %0d, expect 13 (set by child)", the_output4);
        $display("in parent, the_output5: %0d, expect 14 (set by child)", the_output5);
        $display("in parent, the_output6: %0d, expect 15 (set by child)", the_output6);
        $display("in parent, the_output7: %0d, expect 16 (set by child)", the_output7);
    end

    // -------------------------
    // THIS IS THE IMPORTANT BIT
    // -------------------------
    // Note that the signals concatenated for my_input are 0 to 7, but the 
    // output signals are 7 to 0. Why is this??
    child child (
        .my_input({the_input0, the_input1, the_input2, the_input3, the_input4, the_input5, the_input6, the_input7}),
        .my_output({the_output7, the_output6, the_output5, the_output4, the_output3, the_output2, the_output1, the_output0})
    );

endmodule

希望代码非常明显。如上所述，相关位是child模块的实例化。

当运行上面的代码时，显示的输出是我期望的（以及我想要的）：

# in parent, the_output0: 9, expect 9 (set by child)
# in parent, the_output1: 10, expect 10 (set by child)
# in parent, the_output2: 11, expect 11 (set by child)
# in parent, the_output3: 12, expect 12 (set by child)
# in parent, the_output4: 13, expect 13 (set by child)
# in parent, the_output5: 14, expect 14 (set by child)
# in parent, the_output6: 15, expect 15 (set by child)
# in parent, the_output7: 16, expect 16 (set by child)
# in child, my_input[0]: 1, expecting 1 (set by parent)
# in child, my_input[1]: 2, expecting 2 (set by parent)
# in child, my_input[2]: 3, expecting 3 (set by parent)
# in child, my_input[3]: 4, expecting 4 (set by parent)
# in child, my_input[4]: 5, expecting 5 (set by parent)
# in child, my_input[5]: 6, expecting 6 (set by parent)
# in child, my_input[6]: 7, expecting 7 (set by parent)
# in child, my_input[7]: 8, expecting 8 (set by parent)

但我很困惑为什么实例化要求我以不同的方式连接输入与输出的信号。

这有效：

child child (
    // 0 to 7
    .my_input({the_input0, the_input1, the_input2, the_input3, the_input4, the_input5, the_input6, the_input7}),
    // 7 to 0
    .my_output({the_output7, the_output6, the_output5, the_output4, the_output3, the_output2, the_output1, the_output0})
);

但这失败了：

child child (
    // 7 to 0
    .my_input({the_input7, the_input6, the_input5, the_input4, the_input3, the_input2, the_input1, the_input0}),
    // 7 to 0
    .my_output({the_output7, the_output6, the_output5, the_output4, the_output3, the_output2, the_output1, the_output0})
);

这样做：

child child (
    // 0 to 7
    .my_input({the_input0, the_input1, the_input2, the_input3, the_input4, the_input5, the_input6, the_input7}),
    // 0 to 7
    .my_output({the_output0, the_output1, the_output2, the_output3, the_output4, the_output5, the_output6, the_output7})
);

提前感谢任何见解。

Answer 1

交叉兼容性最好的选择是避免使用这样的连接，至少对于输出端口。正如您已经看到的，一些工具以一种方式解释连接，一些工具以不同的方式解释，而一些工具完全禁止这一点。这在SystemVerilog中很常见。

虽然它的代码更多，但这项工作可能适用于所有模拟器而不会出现问题：

logic [4:0] outputs[8];

child child (
  .my_input({the_input0, the_input1, the_input2, the_input3, 
      the_input4, the_input5, the_input6, the_input7}),
  .my_output(outputs)
);

assign the_output0 = outputs[0];
assign the_output1 = outputs[1];
assign the_output2 = outputs[2];
assign the_output3 = outputs[3];
assign the_output4 = outputs[4];
assign the_output5 = outputs[5];
assign the_output6 = outputs[6];
assign the_output7 = outputs[7];

您应该对输入做同样的事情，只是为了更加安全。

为什么在实例化此模块时必须反转输入和输出的串联顺序？

1 个答案: