当我们为同一个变量分配2个值时会发生什么?

时间:2017-06-14 07:01:28

标签: system-verilog system-verilog-assertions

我试图做一个简单的断言,检查两个值是否相等。当我将两个不同的值分配给同一个变量

时,有人可以解释一下这种行为
logic src_sig ;
logic dest_sig;
logic alt_sig;

assign a = src_sig;
assign a = alt_sig;
assign b = dest_sig;

我的断言顺序是:

sequence check_seq(X,Y);
(X == Y);
endsequence

我最初的阻止是:

initial begin

#100 @ (posedge clk) begin
src_sig <= 1;
dest_sig <=1;
alt_sig <= 0;
end

#10 @ (posedge clk) begin
src_sig <=1;
dest_sig <=0;
alt_sig <= 0;
end

#10 @ (posedge clk) begin
src_sig <= 0;
dest_sig <= 0;
alt_sig <= 1;
end

#10 @ (posedge clk) begin
src_sig <= 0;
dest_sig <= 1;
alt_sig <= 1;
end

#30 $finish;
end

我原以为第二项作业会覆盖第一项作业,或者它会分配给src_sigalt_sig。所以要么它应该分别显示2个或4个。但我得到了以下结果(3次违规)。

"testbench.sv", 31: test.check_assert: started at 103ns failed at 103ns
    Offending '(a == b)'
"testbench.sv", 31: test.check_assert: started at 113ns failed at 113ns
    Offending '(a == b)'
"testbench.sv", 31: test.check_assert: started at 133ns failed at 133ns
    Offending '(a == b)'

请解释这里发生了什么?

编辑::完整代码

module test_gcc();
logic clk=0; 
logic src_sig,dest_sig,alt_sig;
assign a = src_sig;
assign a = alt_sig;
assign b = dest_sig;
initial begin 
clk = 0;
forever #1 clk=~clk;
end

sequence check_seq(X,Y);
(X == Y);
endsequence
property check_connection(M,N);
@(posedge clk)
($rose(M)||$rose(N)||$fell(M)||$fell(N)) |-> check_seq(M,N);
endproperty
check_assert : assert property (check_connection(a,b));
initial begin

#100 @ (posedge clk) begin
src_sig <= 1;
dest_sig <=1;
alt_sig <= 0;
end
#10 @ (posedge clk) begin
src_sig <=1;
dest_sig <=0;
alt_sig <= 0;
end

#10 @ (posedge clk) begin
src_sig <= 0;
dest_sig <= 0;
alt_sig <= 1;
end
#10 @ (posedge clk) begin
src_sig <= 0;
dest_sig <= 1;
alt_sig <= 1;
end
#30 $finish;
end
endmodule

1 个答案:

答案 0 :(得分:2)

ab是1位wire,因为您尚未声明它们。 (在Verilog / SV中,除非指定default_nettype none,否则未声明的对象为wire s)。

  

如果您从多个地方驾驶wire,则执行解析功能以评估wire上的值。

在您的情况下,wire a上有两个驱动程序 - 两个assign语句。 initial块确保不同的值始终由两个assign语句驱动,因此线上的已解析值始终为1'bx wire a上的值永远不会改变。

wire b仅由一个assign语句驱动。 initial块确保其值在101ns,111ns和131ns处发生变化。 wire b上的值不会改变为121ns。

您已编写property,以便仅在wire awire b发生更改时才会检查条件

  property check_connection(M,N);
    @(posedge clk)
    ($rose(M)||$rose(N)||$fell(M)||$fell(N)) |-> check_seq(M,N);
  endproperty

wire a永远不会改变且wire b在121ns内没有变化,因此不会在121ns检查条件。