检查具有+/-容差%的时钟频率的最佳方法是什么?

时间:2017-05-11 12:55:20

标签: system-verilog uvm system-verilog-assertions

以下是我目前使用的属性。

property freq_chk (time clk_period , bit disable_chk=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= (clk_period-1)) && 
     (($time - current_time) <= (clk_period+1)) );
endproperty : freq_chk

所以我们在这里考虑时钟周期中的容差限制为+/- 1。 通过公差百分比并检查频率的最佳方法是什么。

我正在寻找下面的内容(这样做不起作用,只是为了展示我正在看的内容。)

property freq_chk_with_tol (time clk_period , bit disable_chk=0, int tolerance=0);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100) )) - 1)) && 
     (($time - current_time) <= ( (clk_period * (1 + (tolerance/100) )) + 1)) );
endproperty : freq_chk_with_tol

检查具有+/-容差%?

的时钟频率的最佳方法是什么?

2 个答案:

答案 0 :(得分:1)

正如Greg建议的那样,将整数值更改为real对我来说是个窍门。

以下是工作代码。

property freq_chk_tol (time clk_period , bit disable_chk=0, real tolerance=0.00);
  time current_time; 
  disable iff ( disable_chk )
  ('1, current_time = $time) |=> 
   ( (($time - current_time) >= ( (clk_period * (1 - (tolerance/100.00) )) - 1)) && 
     (($time - current_time) <= ( (clk_period * (1 + (tolerance/100.00) )) + 1)) );
endproperty : freq_chk_tol

答案 1 :(得分:0)

为什么要使用断言?使用行为代码会不会更容易?

time clk_margin = <set it to whatever value you need>;   // calculate it once, don't calculate on the fly
time last_clk_tick;
always_ff @(posedge clk) begin
  assert (abs($time - last_clk_tick) < clk_margin);  // abs() is a user function return the absolute value
  last_clk_tick = $time;
end