我已经创建了一个包含两个模块的模块，第一个是初始化内存，第二个是检查从内存中获取的一些值。这是我的代码
module correct(clk,reset,state,en_vs_w,c_vs_wt,
data_in1,data_in0,j_st,k_st,e,i_st,m_st);
input clk,reset;
output [2:0]state;
output en_vs_w,e;
output [2:0]c_vs_wt;
input [2:0]data_in1;
input [2:0]data_in0;
input [3:0]j_st;
input [3:0]k_st;
output reg [2:0]i_st;
output reg [3:0]m_st;
wire en;
wire inc_m;
wire [2:0]check;
check_1 c_1(.clk(clk),.reset(reset),.i_st(i_st),.en(en),
.data_in1(data_in1),.data_in0(data_in0),
.check(check),.j_st(j_st),.k_st(k_st),.m_st(m_st),.inc_m(inc_m),.e(e));
valid_state_1 v_s_1(.clk(clk),.reset(reset),.i_st(i_st),.m_st(m_st),
.state(state),.en(en),.check(check),
.inc_m(inc_m),.c_vs_wt(c_vs_wt),.en_vs_w(en_vs_w));
endmodule
/////////////////////////////
module check_1(clk,reset,i_st,en,data_in1,
data_in0,check,j_st,k_st,m_st,inc_m,e);
input wire[2:0]i_st;
input en;
input clk;
input wire[3:0]j_st;
input wire[3:0]k_st;
input wire[3:0]m_st;
input reset;
input wire[2:0]data_in0;
input wire[2:0]data_in1;
output reg [2:0]check;
output reg inc_m;
reg [12:0]arr[0:7];
output reg e ;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3 ,S4 = 4 ;
// Declare max address (it could be less words)
parameter MAXADDRESS = 3'b111;
parameter FILLINGVALUE_A = 12'hFFF;
//parameter FILLINGVALUE_PM = 3'b111;
reg [2:0] i;
reg [2:0] state;
always @ (posedge clk) begin
if (reset)
begin
state <= S0;
e<=0;
end
else if (e==0)
begin
case (state)
S0: begin
i <= 3'b0;
//j<= 4'b0;
state <= S1;
end
S1: begin
arr[i] <= FILLINGVALUE_A;
//PM[i] <= FILLINGVALUE_PM;
if (i == MAXADDRESS) begin
state <= S2;
end
else begin
i <= i + 3'b001;
state <= S1;
end
end
S2: begin
e<=1;
//inc_c=1;
arr[0][2:0] <= 3'b0;
end
endcase
end
else if(en==1 && e==1)
begin
arr[i_st+3'b001][j_st +:3]<= data_in0;
arr[i_st+3'b001][k_st +:3] <= data_in1;
inc_m <= 1;
end
else if (en==0 && e==1)
begin
check<= arr[i_st][m_st +:3] ;
end
end
endmodule
////////////////////////////
module valid_state_1(clk,reset,i_st,m_st,
state,en,check,inc_m,c_vs_wt,en_vs_w);
input clk,reset;
input [2:0]check;
input inc_m;
output [2:0]i_st;
output [3:0]m_st;
output reg en ,en_vs_w;
output reg[2:0] state;
output reg [2:0]c_vs_wt;
reg [2:0]i;
reg [3:0]m;
always @ (posedge clk)
begin
if (reset)
begin
m <= 4'b0000;
i <= 3'b000;
en <=0;
end
end
always @ (check)
begin
if (m<=4'b1011 )
begin
if (check<=3'b110)
begin state <= check;
m<= m+ 4'b0011;
en<= 1'bx; end
else
begin m<= m + 4'b0011;
en<= 0;
en_vs_w<= 1;
c_vs_wt<= 3'b000;
end
end
else if (m==4'b1100 && i < 3'b011)
begin
i<= i+3'b001;
m<= 4'b00000;
en<=1'bx;
end
else if (inc_m == 1 && i < 3'b011)
begin
m <= m + 4'b0011;
en<= 0;
en_vs_w<= 1;
c_vs_wt<= 3'b000;
end
else if (i == 3'b011)
begin
en<=1'bx;
m<= 4'bxxxx;
i <= 3'bxxx;
end
end
assign m_st =m;
assign i_st = i;
endmodule
///////////////////////////// 时钟和重置对于检查模块工作正常但是它对于valid_state块没有正常工作。它没有设置＆＃34; m＆＃34;和＆＃34;我＆＃34; as＆＃34; 00000＆＃34; ＆安培; ＆＃34; 000＆＃34;分别和我无法理解它的错误。个别工作正常，但没有工作＆＃34;纠正＆＃34;模块