错误：Modelsim上的TopLevel vhdl

Question

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL; 
entity TopLevel is
Port ( reset : in std_logic;
clock : in std_logic;
coin : in std_logic;
push : in std_logic;
count1 : out std_logic_vector(15 downto 0)

); 
end TopLevel;
architecture Modular of TurnstileDetector is
signal unlock : std_logic;
begin
controller: entity   TurnstileDetectorController
Port map ( reset => reset,
clock => clock,
coin => coin,
push => push,
unlock => unlock 
);
counter: entity work.counter
Port map ( reset => reset,
clock => clock,
cen => unlock,
q => count1
);
end architecture Modular; 

错误： **错误：（vcom-11）找不到work.turnstiledetector。

**错误：C：/Modeltech_pe_edu_10.4a/examples/TopLevel.vhd（14）：VHDL编译器退出

Answer 1

您需要将architecture Modular of TurnstileDetector is更改为architecture Modular of TopLevel is