在fpga spartan 6板上连接ddr2 RAM时发生错误 港口有非法连接。此端口连接到输入缓冲区和其他组件。
module atlys_ddr_test(
output DDR2CLK_P,
output DDR2CLK_N,
output DDR2CKE,
output DDR2RASN,
output DDR2CASN,
output DDR2WEN,
inout DDR2RZQ,
inout DDR2ZIO,
output [2:0] DDR2BA,
output [12:0] DDR2A,
inout [15:0] DDR2DQ,
inout DDR2UDQS_P,
inout DDR2UDQS_N,
inout DDR2LDQS_P,
inout DDR2LDQS_N,
output DDR2LDM,
output DDR2UDM,
output DDR2ODT,
output reg [11:0] count,
input clk, // 100 MHz oscillator = 10ns period (top level pin)
input rst
);
// Instantiate the Unit Under Test (UUT)
ddr_interface ddr_interface (
.DDR2CLK_P(DDR2CLK_P),
.DDR2CLK_N(DDR2CLK_N),
.DDR2CKE(DDR2CKE),
.DDR2RASN(DDR2RASN),
.DDR2CASN(DDR2CASN),
.DDR2WEN(DDR2WEN),
.DDR2RZQ(DDR2RZQ),
.DDR2ZIO(DDR2ZIO),
.DDR2BA(DDR2BA),
.DDR2A(DDR2A),
.DDR2DQ(DDR2DQ),
.DDR2UDQS_P(DDR2UDQS_P),
.DDR2UDQS_N(DDR2UDQS_N),
.DDR2LDQS_P(DDR2LDQS_P),
.DDR2LDQS_N(DDR2LDQS_N),
.DDR2LDM(DDR2LDM),
.DDR2UDM(DDR2UDM),
.DDR2ODT(DDR2ODT),
.clk(clk),
.c3_p0_cmd_instr(c3_p0_cmd_instr),
.c3_p0_cmd_bl(c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr(c3_p0_cmd_byte_addr),
.c3_p0_wr_mask(c3_p0_wr_mask),
.c3_p0_wr_data(c3_p0_wr_data),
.c3_p0_wr_count(c3_p0_wr_count),
.c3_p0_rd_data(c3_p0_rd_data),
.c3_p0_rd_count(c3_p0_rd_count),
.c3_p0_rd_en(c3_p0_rd_en),
.c3_p0_rd_empty(c3_p0_rd_empty),
.c3_p0_wr_en(c3_p0_wr_en),
.c3_p1_cmd_instr(c3_p1_cmd_instr),
.c3_p1_cmd_bl(c3_p1_cmd_bl),
.c3_p1_cmd_byte_addr(c3_p1_cmd_byte_addr),
.c3_p1_wr_mask(c3_p1_wr_mask),
.c3_p1_wr_count(c3_p1_wr_count),
.c3_p1_wr_data(c3_p1_wr_data),
.c3_p1_rd_data(c3_p1_rd_data),
.c3_p1_rd_count(c3_p1_rd_count),
.c3_p1_rd_en(c3_p1_rd_en),
.c3_p1_rd_empty(c3_p1_rd_empty),
.c3_p1_wr_en(c3_p1_wr_en),
.c3_p1_cmd_en(c3_p1_cmd_en),
.c3_p0_cmd_en(c3_p0_cmd_en),
.c3_calib_done(c3_calib_done),
.reset(reset),
.c3_clk0(c3_clk0)
//.clk2(CLK_OUT2)
);
// Here we're feeding the user clock into the port FIFOs. You will not want to do this if you are running
// the FIFOs (three per port!) in different clock domains, but then you'll need to bring clocks in from elsewhere.
.c3_p0_cmd_clk (clk), // A clock!
.c3_p0_cmd_en (c3_p0_cmd_en),
.c3_p0_cmd_instr (c3_p0_cmd_instr),
.c3_p0_cmd_bl (c3_p0_cmd_bl),
.c3_p0_cmd_byte_addr (c3_p0_cmd_byte_addr),
.c3_p0_cmd_empty (c3_p0_cmd_empty),
.c3_p0_cmd_full (c3_p0_cmd_full),
.c3_p0_wr_clk (clk), // A clock!
.c3_p0_wr_en (c3_p0_wr_en),
.c3_p0_wr_mask (c3_p0_wr_mask),
.c3_p0_wr_data (c3_p0_wr_data),
.c3_p0_wr_full (c3_p0_wr_full),
.c3_p0_wr_empty (c3_p0_wr_empty),
.c3_p0_wr_count (c3_p0_wr_count),
.c3_p0_wr_underrun (c3_p0_wr_underrun),
.c3_p0_wr_error (c3_p0_wr_error),
.c3_p0_rd_clk (clk), // A clock!
.c3_p0_rd_en (c3_p0_rd_en),
.c3_p0_rd_data (c3_p0_rd_data),
.c3_p0_rd_full (c3_p0_rd_full),
.c3_p0_rd_empty (c3_p0_rd_empty),
.c3_p0_rd_count (c3_p0_rd_count),
.c3_p0_rd_overflow (c3_p0_rd_overflow),
.c3_p0_rd_error (c3_p0_rd_error),
.c3_p1_cmd_clk (clk), // A clock!
.c3_p1_cmd_en (c3_p1_cmd_en),
.c3_p1_cmd_instr (c3_p1_cmd_instr),
.c3_p1_cmd_bl (c3_p1_cmd_bl),
.c3_p1_cmd_byte_addr (c3_p1_cmd_byte_addr),
.c3_p1_cmd_empty (c3_p1_cmd_empty),
.c3_p1_cmd_full (c3_p1_cmd_full),
.c3_p1_wr_clk (clk), // A clock!
.c3_p1_wr_en (c3_p1_wr_en),
.c3_p1_wr_mask (c3_p1_wr_mask),
.c3_p1_wr_data (c3_p1_wr_data),
.c3_p1_wr_full (c3_p1_wr_full),
.c3_p1_wr_empty (c3_p1_wr_empty),
.c3_p1_wr_count (c3_p1_wr_count),
.c3_p1_wr_underrun (c3_p1_wr_underrun),
.c3_p1_wr_error (c3_p1_wr_error),
.c3_p1_rd_clk (clk), // A clock!
.c3_p1_rd_en (c3_p1_rd_en),
.c3_p1_rd_data (c3_p1_rd_data),
.c3_p1_rd_full (c3_p1_rd_full),
.c3_p1_rd_empty (c3_p1_rd_empty),
.c3_p1_rd_count (c3_p1_rd_count),
.c3_p1_rd_overflow (c3_p1_rd_overflow),
.c3_p1_rd_error (c3_p1_rd_error)
);