Question

我尝试使用define来简化编写，所有参数都是真正编写的

//...
parameter  BLEZ = 1001011;
parameter  BLTZ = 1001100;
parameter  SRA  = 1001101;

`define R_type1 ((op == MOVA)||(op == MOVB)||(op == ADD)||(op == SUB)||(op == AND)||(op == OR)||(op == XOR)||(op == NOT)||(op == SLT))
`define R_type2 ((op == LSL)||(op == LSR)||(op == SRA))
`define JR_type ((op == JMR))
`define J_type  ((op == JMP))
`define I_type  ((op == ADI)||(op == SBI)||(op == ANI)||(op == ORI)||(op == XRI)||(op == AIU)||(op == SIU)(op == JML))
`define LW  ((op == LD))
`define SW  ((op == ST))
`define Branch  ((op == BZ)||(op == BNZ)||(op == BGEZ)||(op == BGTZ)||(op == BLEZ)||(op == BLTZ))

always@(op)
begin
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
MemWrite_id    = 1;//(`SW);
MemRead_id     = (`LW);
MemToReg_id    = (`LW);
ALUSrcA_id     = (`R_type2);
ALUSrcB_id     = (`I_type);
PCSource       = {`JR_type,`J_type,Z};
end

我认为逻辑层面没有任何问题，但它总是会产生一些错误像这样：

RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                        |
ncvlog: *E,EXPRPA (Decode_Unit.v,71|56): expecting a right parenthesis (')') [4.3][9.7(IEEE)].
(`define macro: I_type [Decode_Unit.v line 64], file: Decode_Unit.v line 71)
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,EXPSMC (Decode_Unit.v,71|58): expecting a semicolon (';') [9.2.2(IEEE)].
RegWrite_id    = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,NOTSTT (Decode_Unit.v,71|58): expecting a statement [9(IEEE)].
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
               |
ncvlog: *E,EXPLPA (Decode_Unit.v,72|15): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                        |
ncvlog: *E,EXPRPA (Decode_Unit.v,72|56): expecting a right parenthesis (')') [4.3][9.7(IEEE)].
(`define macro: I_type [Decode_Unit.v line 64], file: Decode_Unit.v line 72)
RegDst_id      = ((`LW)||(`R_type1)||(`R_type2)||(`I_type));
                                                          |
ncvlog: *E,EXPSMC (Decode_Unit.v,72|58): expecting a semicolon (';') [12.1.2][7.1(IEEE)].
MemWrite_id    = 1;//(`SW);
               |
ncvlog: *E,EXPLPA (Decode_Unit.v,73|15): expecting a left parenthesis ('(') [12.1.2][7.1(IEEE)].
MemRead_id     = (`LW);

并且所有参数都是真正写的

它令人困惑.... 请给我一些指导

Answer 1

您忘记了||宏中最后两个字词之间的I_type运算符。

另请注意，如果您希望将参数解释为二进制数，则必须在它们前面添加'b，例如'b1010是二进制数字10，{{1}是一千一十。

Answer 2

正如Unn已经指出的那样，I_type缺少一个||并且需要指定基数（否则它被假定为十进制）。

示例'b1010是二进制数字10，而1010是十分之一。

此外，正如您所经历的那样`define很难调试。请注意，`define基于编译顺序应用于全局空间。这意味着另一个模块可以使用相同的宏而不定义它，如果它是后编译的，这可能导致混淆并且错误未正确完成。建议避免（或至少最小化）在RTL中使用`define。

根据您的代码，我建议您将`define更改为wire。它将合成相同但更容易调试。我在理智上离开了|| bug来演示。

wire R_type1 = ((op == MOVA)||(op == MOVB)||(op == ADD)||(op == SUB)||(op == AND)||(op == OR)||(op == XOR)||(op == NOT)||(op == SLT));
wire R_type2 = ((op == LSL)||(op == LSR)||(op == SRA));
wire JR_type = ((op == JMR));
wire J_type  = ((op == JMP));
wire I_type  = ((op == ADI)||(op == SBI)||(op == ANI)||(op == ORI)||(op == XRI)||(op == AIU)||(op == SIU)(op == JML));
wire LW      = ((op == LD));
wire SW      = ((op == ST));
wire Branch  = ((op == BZ)||(op == BNZ)||(op == BGEZ)||(op == BGTZ)||(op == BLEZ)||(op == BLTZ));

always@* // IMPORTANT :: use '*', not 'op'
begin
  RegWrite_id    = ((LW)||(R_type1)||(R_type2)||(I_type));
  RegDst_id      = ((LW)||(R_type1)||(R_type2)||(I_type));
  MemWrite_id    = 1;//(SW);
  MemRead_id     = (LW);
  MemToReg_id    = (LW);
  ALUSrcA_id     = (R_type2);
  ALUSrcB_id     = (I_type);
  PCSource       = {JR_type,J_type,Z};
end

组合总是块应该使用自动灵敏度; always@*或同义always@(*)。自IEEE1364-2001以来，支持自动灵敏度。指定灵敏度列表仅建议您遵循严格的IEEE1364-1995，或者在行为模块中排除不合成的信号。

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