我正在尝试用VHDL实现Booth算法。到目前为止，我已经实现了ALU，时钟和移位寄存器。现在我想使用这些模块来实现最后一个模块，这是实际的算法，但我不知道如何在其他模块中使用这些模块。
这是我的alu模块：
library ieee;
use ieee.numeric_bit.all;
entity alu is
port ( bus_a : in bit_vector(7 downto 0);
bus_b : in bit_vector(7 downto 0);
state : in bit_vector (2 downto 0);
out_c : out bit_vector(7 downto 0));
end alu;
architecture behave of alu is
begin
process(bus_a, bus_b, state)
begin
case state is
when "000" =>
out_c<= bit_vector(unsigned(bus_a) + unsigned(bus_b)); --addition
when "001" =>
out_c<= bit_vector(unsigned(bus_a) - unsigned(bus_b)); --subtraction
when "010" =>
out_c<= bit_vector(unsigned(bus_a) - 1); --sub 1
when "011" =>
out_c<= bit_vector(unsigned(bus_a)+ 1); --add 1
when "100" =>
out_c<= bus_a and bus_b; --AND gate
when "101" =>
out_c<= bus_a or bus_b; --OR gate
when "110" =>
out_c<= not bus_a ; --NOT gate
when "111" =>
out_c<= bus_a xor bus_b; --XOR gate
when others =>
NULL;
end case;
end process;
end architecture behave;
我有移位寄存器：
entity shift_reg is
generic(n:integer:=8; delay:time :=10ns);
port(parallel_in: in bit_vector(n-1 downto 0);
parallel_out: out bit_vector(n-1 downto 0);
clock, reset, load, shift, serial_in: in bit;
serial_out: out bit);
end shift_reg;
architecture behave of shift_reg is
begin
process(clock, reset)
variable temp: bit_vector(n-1 downto 0);
begin
if reset='0' then
temp:=(others=>'0');
elsif clock='1' and clock'event and clock'last_value='0' then
if shift='1' then
serial_out <= temp(0) after delay;
temp:= temp sll 1;
temp(n-1):= serial_in;
elsif load='1' then
temp:=parallel_in;
end if;
end if;
parallel_out <= temp after delay;
end process;
end architecture behave;
和时钟发生器：
ENTITY clk_gen IS
GENERIC(t_high: TIME:=30ns; t_period: TIME:=50ns; t_reset: TIME:=10ns);
PORT(clock: OUT BIT:='1'; reset : OUT BIT);
END clk_gen;
ARCHITECTURE behave OF clk_gen IS
BEGIN
reset<='0', '1' AFTER t_reset;
PROCESS
BEGIN
clock<='1', '0' AFTER t_high;
WAIT FOR t_period;
END PROCESS;
END ARCHITECTURE;
因为我是VHDL的新手，我不知道如何使用这些函数（语法等），这是我在最终算法中所需要的。 关于如何将这些模块集成到第三个模块中的任何帮助，这将是booth算法，将非常感激。提前谢谢！
修改 这里我有部分实例化的Booth算法实现：
entity booth_mul is
generic(x : integer := 8);
port(
bus_x : in bit_vector((x - 1) downto 0);
bus_y : in bit_vector((x - 1) downto 0);
out_z : out bit_vector((2*x - 1) downto 0));
end booth_mul;
architecture behave of booth_mul is
component alu is
port(bus_a : in bit_vector(7 downto 0);
bus_b : in bit_vector(7 downto 0);
state : in bit_vector (2 downto 0);
out_c : out bit_vector(7 downto 0));
end component;
component shift_reg is
generic(n: integer:=8; delay: time:=10ns);
port(parallel_in: in bit_vector(n-1 downto 0);
parallel_out: out bit_vector(n-1 downto 0);
clock, reset, load, shift, serial_in: in bit;
serial_out: out bit);
end component;
begin
process(bus_x, bus_y, out_z)
variable st: bit_vector
begin
for i in 0 to x loop
case st is
when "00"
--I want here to do an arithmetic shift, behaviour that is implemented in my shift_reg, can I call it somehow or how should I use it ?
end process;
end architecture behave;
我在评论中添加了我想要实现的内容，但对我来说还不清楚。