每当灵敏度列表的输入是一个变量(它是模块的输入; FPGA上的一个按钮)时,无论这个变量的值是否发生变化,代码块都会被执行,甚至虽然always块中的代码块只应在作为灵敏度列表中的参数给出的变量值发生变化时执行;因此被称为敏感性列表。
代码块如下:
always @(in)
begin
count = count + 1;
end
in:从FPGA上的按钮获取的输入
我们的代码块在某种程度上是错误的,还是灵敏度列表只是采取了构造或者是否会出现?
答案 0 :(得分:0)
我不熟悉编写异步逻辑的规则/做法,但这是处理按钮按下时的2美分:
尝试编写去抖模块以检测何时按下按钮,然后使用去抖模块的结果作为计数器的启用信号。在这种情况下,计数器的灵敏度列表将基于posedge clk。
这里有一个explanation,说明你需要去抖模块的原因。
去抖模块的工作原理如下:让我们说要注册一个按钮按下按钮按住3ms并再释放3ms。 (随意玩这个时间。)因此,我们需要两个计数器:按下并释放。按下的计数器计数到3ms然后设置条件以允许释放计数器开始计数。一旦释放计数器达到3ms,则该按钮已被注册为按下。
module debounce(
clk,
button_input,
button_pressed
);
// Input and output ports
input clk, button_input;
output button_pressed;
reg button_pressed;
// Signals for pressed and released counters
reg [15:0] pressed_out, pressed_next_out, released_out, released_next_out;
reg pressed_enable, pressed_reset, released_enable, released_reset;
reg pressed_ok, released_ok;
// Counter for when button is pressed down
// Increment counter
always @ (*) begin
if (button_input) begin
pressed_next_out = pressed_out + 1'b1;
end else begin
pressed_next_out = 16'h00000;
end
end
// Flop incremented value
always @ (posedge clk)
pressed_out <= pressed_next_out;
// Check if button was pressed (3ms)
always @ (posedge clk) begin
if (&pressed_out) begin
pressed_ok <= 1;
end else if (released_ok) begin
pressed_ok <= 0;
end
end
// Counter for when button is released
// Increment counter
always @ (*) begin
if (~button_input && pressed_ok) begin
released_next_out = released_out + 1'b1;
end else begin
released_next_out = 16'b0;
end
end
// Flop incremented value
always @ (posedge clk)
released_out <= released_next_out;
// Check if button was released (3ms)
always @ (posedge clk) begin
if (&released_out) begin
released_ok <= 1;
end else begin
released_ok <= 0;
end
end
// Check if button was pressed and released
always @ (posedge clk)
button_pressed <= pressed_ok && released_ok;
endmodule