Question

我接受了这个问题作为面试前的问题＆＃34;绘制图表并编写满足以下要求的模块的VHDL代码：一个。完全同步。湾11条总线之间的复用器，每条总线的宽度为8位。 C。有2个周期的延迟。 d。针对最大时钟频率进行了优化。＆＃34;

我一直在尝试自己阅读我在大学里所做的旧笔记和作业，但我认为我并没有想到这一点。我的代码如下所示：

 library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity Mux is
port(

 A:  in STD_LOGIC_vector(7 downto 0);
  B:  in STD_LOGIC_vector(7 downto 0);
  C:  in STD_LOGIC_vector(7 downto 0);
  D:  in STD_LOGIC_vector(7 downto 0);
  E:  in STD_LOGIC_vector(7 downto 0);
  F:  in STD_LOGIC_vector(7 downto 0);
  G:  in STD_LOGIC_vector(7 downto 0);
  H:  in STD_LOGIC_vector(7 downto 0);
  I:  in STD_LOGIC_vector(7 downto 0);
  J:  in STD_LOGIC_vector(7 downto 0);
  K:  in STD_LOGIC_vector(7 downto 0);
 S0: in std_LOGIC_vector(3 downto 0);

 Z: out STD_LOGIC_vector(7 downto 0)
);
 end Mux;
architecture func of Mux is
begin
process (A,B,C,D,E,F,G,H,I,J,K,S0)
begin

    if S0="0001" then
        Z<= A;
    elsif S0="0010" then
        Z<= B;
    elsif S0="0011" then
        Z<= C;
    elsif S0="0100" then
        Z<= D;
    elsif S0="0101" then
        Z<= E;
    elsif S0="0110" then
        Z<= F;
    elsif S0="0111" then
        Z<= G;
    elsif S0="1000" then
        Z<= H;
    elsif S0="1001" then
        Z<= I;
    elsif S0="1010" then
        Z<= J;
    elsif S0="1011" then
        Z<= K;  
    else 
        Z<=A;
    end if;


end process;
end func;

这是我第二个文件的代码：

 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
 use IEEE.std_logic_arith.all;
 entity mux11test is
 end entity mux11test;
 architecture test of mux11test is
  signal    T_A:  STD_LOGIC_vector(7 downto 0):="00000001";
   signal    T_B:  STD_LOGIC_vector(7 downto 0):="00000010";
  signal    T_C:  STD_LOGIC_vector(7 downto 0):="00000011";
  signal    T_D:  STD_LOGIC_vector(7 downto 0):="00000100";
  signal    T_E:  STD_LOGIC_vector(7 downto 0):="00000101";
  signal    T_F:  STD_LOGIC_vector(7 downto 0):="00000110";
  signal    T_G:  STD_LOGIC_vector(7 downto 0):="00000111";
  signal    T_H:  STD_LOGIC_vector(7 downto 0):="00001000";
  signal    T_I:  STD_LOGIC_vector(7 downto 0):="00001001";
  signal    T_J:  STD_LOGIC_vector(7 downto 0):="00001010";
  signal    T_K:  STD_LOGIC_vector(7 downto 0):="00001011";

   signal    T_S: STD_LOGIC_vector( 3 downto 0);
 signal    T_Z:  STD_LOGIC_vector(7 downto 0);

component mux11 IS
port(

 A:  in STD_LOGIC_vector(7 downto 0);
  B:  in STD_LOGIC_vector(7 downto 0);
  C:  in STD_LOGIC_vector(7 downto 0);
  D:  in STD_LOGIC_vector(7 downto 0);
  E:  in STD_LOGIC_vector(7 downto 0);
  F:  in STD_LOGIC_vector(7 downto 0);
  G:  in STD_LOGIC_vector(7 downto 0);
  H:  in STD_LOGIC_vector(7 downto 0);
  I:  in STD_LOGIC_vector(7 downto 0);
  J:  in STD_LOGIC_vector(7 downto 0);
  K:  in STD_LOGIC_vector(7 downto 0);
 S0: in std_LOGIC_vector(3 downto 0);

 Z:  out STD_LOGIC_vector(7 downto 0)
  ); 
END COMPONENT ;
signal clk : std_LOGIC;
constant clk_period: time:=100ns;
begin

umux: Mux11 port map(T_A,T_B,T_C,T_D,T_E,T_F,T_G,T_H,T_I,T_J,T_K,T_S,T_Z);
clk_process:process 
begin
clk<='0';
wait for clk_period/2;
clk <='1';
wait for clk_period/2;
end process;
PROCESS
begin
if T_S="0001" then
    T_Z <= T_A ;
elsif  T_S="0010" then  
T_Z <= T_B ; wait for 100 ns; 
elsif  T_S="0011" then
T_Z <= T_C ; wait for 100 ns; 
elsif  T_S="0100" then
T_Z  <= T_D ; wait for 100 ns;
elsif  T_S="0101" then
T_Z  <=T_E ; wait for 100 ns;
elsif  T_S="0110" then
T_Z <=  T_F ; wait for 100 ns;
    elsif  T_S="0111" then
T_Z  <= T_G ; wait for 100 ns;
    elsif  T_S="1000" then
T_Z  <= T_H ; wait for 100 ns;
elsif  T_S="1001" then
T_Z  <= T_I ; wait for 100 ns;
elsif  T_S="1010" then
T_Z  <= T_J ; wait for 100 ns;
elsif  T_S="1011" then
T_Z <= T_K ; wait for 100 ns;


wait;

end if;
end PROCESS;

end architecture test;

有没有人可以告诉我，如果我是在正确的道路上，如果这是完全同步的，我将如何开始实施或确定2个周期的延迟？

Answer 1

我试着写一个明确的答案来帮助你。

首先，您需要在设计中使用时钟，然后将其称为clk。

entity Mux is
port(

  clk: in std_logic;
  A:  in STD_LOGIC_vector(7 downto 0);
  B:  in STD_LOGIC_vector(7 downto 0);
  C:  in STD_LOGIC_vector(7 downto 0);
  D:  in STD_LOGIC_vector(7 downto 0);
  E:  in STD_LOGIC_vector(7 downto 0);
  F:  in STD_LOGIC_vector(7 downto 0);
  G:  in STD_LOGIC_vector(7 downto 0);
  H:  in STD_LOGIC_vector(7 downto 0);
  I:  in STD_LOGIC_vector(7 downto 0);
  J:  in STD_LOGIC_vector(7 downto 0);
  K:  in STD_LOGIC_vector(7 downto 0);
  S0: in std_LOGIC_vector(3 downto 0);

  Z: out STD_LOGIC_vector(7 downto 0));

end Mux;

使用同步过程时的想法是始终在时钟边缘更新值。让我们说上升的边缘。因此，您的流程必须仅对您的输入clk敏感。

P : PROCESS (clk)
BEGIN
   IF (rising_edge(clk)) THEN
     ...
   END IF;
END PROCESS;

关于您的多路复用器，您的想法很好。但我建议使用 CASE 语句，因为它比 IF ELSIF 更容易阅读。

CASE S0 IS
    WHEN "0001"  => Z <= A;
    WHEN "0010"  => Z <= B;
    ...
    WHEN "1011"  => Z <= K;
END CASE;

编辑：因为我忘了谈论2个周期的延迟，我会说两个字。你需要两个中间信号（即Z_i和Z_ii）。 Z_ii在一个时钟周期后取Z_i，Z在一个时钟周期后取Z_ii。

Z_ii <= Z_i;
Z    <= Z_ii;

当然，你需要在你的过程中驾驶Z_i（而不是Z）。

VHDL：11条总线之间的多路复用器，8位宽输出

1 个答案: