DS-5 eclipse调试卡在waitForTargetToStop上

时间:2016-10-29 01:10:43

标签: eclipse arm ds-5

首先,我遵循DS-5 start demo并可以在ARM FVP上正确调试我的代码 - > VE_Coretex_A9x1。

然后我按照link启用NEON,它需要在构建中设置CPU目标,axf文件已正确构建但调试器停止工作。连接到主板后CA9_FVP挂起。它显示waitForTargetToStop

Connected to stopped target ARM FVP (Installed with DS-5) - VE_Cortex_A9x1 Execution stopped at: S:0x00000000 loadfile "test.axf" S:0x00000000 DCI 0xe7ff0010 ; ? Undefined Loaded section ER_RO: S:0x80000000 ~ S:0x80002C0B (size 0x2C0C) Loaded section ER_RW: S:0x80002C0C ~ S:0x80002C1F (size 0x14) Entry point S:0x80000000 cd "Documents\DS-5 Workspace" Semihosting server socket created at port 8001 Semihosting enabled automatically due to semihosting symbol detected in image 'math_neon.axf' Working directory "Documents\DS-5 Workspace" set debug-from main start Starting target with image test.axf Running from entry point wait

作为调试的结果:

_fp_init
S:0x80002B88 : MOV      r0,#0x3000000
S:0x80002B8C : VMSR     FPSCR,r0                  --> this line will cause PC jump to 0x00000004 and them stuck

S:0x00000000 : DCI      0xe7ff0010 ; ? Undefined
S:0x00000004 : STMDA    r0,{r11,sp-pc}
S:0x00000008 : DCI      0xe7ff0010 ; ? Undefined
S:0x0000000C : STMDA    r0,{r11,sp-pc}
S:0x00000010 : DCI      0xe7ff0010 ; ? Undefined
S:0x00000014 : STMDA    r0,{r11,sp-pc}

2 个答案:

答案 0 :(得分:1)

转到项目属性> C / C ++构建> 设置> 工具设置> ARM链接器> 图像布局 然后将图像入口点(--entry)填充为 Vectors

注意:这是针对在Eclipse上运行的DS5

答案 1 :(得分:1)

我遇到了同样的问题。发生的事情是在进入main()函数之前引发了一个异常。如果您从入口点(调试配置配置,调试器选项卡)进行调试,并逐步执行asm代码,则当fp_init()函数尝试写入FPSCR寄存器时,您会看到它引发了异常。原因是必须先启用完全访问权限,然后代码才能写入FPSCR寄存器。

一种解决方案是编写自己的fp_init()函数。我通过从DS-5随附的fireworks_A9-FVP_AC5教程项目中的“ startup.s”文件中复制VFP / NEON激活代码来编写我的代码。我想保留C文件,因此向我的项目添加了一个“ startup.c”文件,内容如下。那对我有用。

__asm void _fp_init(void) {
  IF {TARGET_FEATURE_NEON} || {TARGET_FPU_VFP}

  ; Enable access to NEON/VFP by enabling access to Coprocessors 10 and 11.
  ; Enables Full Access i.e. in both privileged and non privileged modes
        MRC     p15, 0, r0, c1, c0, 2     ; Read Coprocessor Access Control Register (CPACR)
        ORR     r0, r0, #(0xF << 20)      ; Enable access to CP 10 & 11
        MCR     p15, 0, r0, c1, c0, 2     ; Write Coprocessor Access Control Register (CPACR)
        ISB

  ; Switch on the VFP and NEON hardware
        MOV     r0, #0x40000000
        VMSR    FPEXC, r0                   ; Write FPEXC register, EN bit set

  ENDIF
}