Question

我必须编写一个程序，在一个序列的每个时钟脉冲处改变LED序列。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity REG_LED is
 PORT(CLK:      IN  std_logic;              -- CLK input
 LEDS:      Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
 SIGNAL Temp:   std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal
BEGIN

CLK_Process:    PROCESS (CLK)   -- begin 
BEGIN 

if rising_edge(CLK) Then
       Temp <= Temp + 1 ;   
END IF;

iF TEMP > "1000" THEN
    Temp <= "XXXX";
End IF;

END PROCESS ;

LED_PROCESS: Process (Temp) --

BEGIN

    Case Temp is

        When "0000" =>
            LEDS <= "11111";
        When "0001" =>
            LEDS <= "00001";
        When "0010" =>
            LEDS <= "00001";
        When "0011" =>
            LEDS <= "11111";
        When "0100" =>
            LEDS <= "00000";
        When "0101" =>
            LEDS <= "11111";
        When "0110" =>
            LEDS <= "00100";
        When "0111" =>
            LEDS <= "01010";
        When "1000" =>
            LEDS <= "10001";
        When others => 
            LEDS <= "10001";
    End Case;               

End Process;
END behavioral;

这看起来更像你期望的吗？它模拟但我无法测试代码的合成，因为我现在有硬件来测试它。或者，如果因为我是VHDL的新手而有办法，我还没有找到如何测试它。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;


entity REG_LED is
PORT(CLK:       IN  std_logic;              -- CLK input
     LEDS:      Out std_logic_vector (4 downto 0):= "11111"); -- initialise output
End REG_LED;

ARCHITECTURE behavioral OF REG_LED IS
SIGNAL Temp:    integer range 0 to 9:= 0; -- initailise comparison signal
BEGIN

    CLK_Process:    PROCESS (CLK)   -- begin 
    BEGIN 

    if rising_edge(CLK) Then
        if Temp = 8 then
            Temp <= 0; -- State Count Reset
        else
            Temp <= Temp + 1 ; -- State Count
        End if;

    END IF;

    END PROCESS ;

    LED_PROCESS: Process (Temp) -- LED Outputs based on Temp count

    BEGIN

        Case Temp is

            When 0 =>
                LEDS <= "11111"; -- S0
            When 1 =>
                LEDS <= "00001"; -- S1
            When 2 =>
                LEDS <= "00001"; -- S2
            When 3 =>
                LEDS <= "11111"; -- S3
            When 4 =>
                LEDS <= "00000"; -- S4
            When 5 =>
                LEDS <= "11111"; -- S5
            When 6 =>
                LEDS <= "00100"; -- S6
            When 7 =>
                LEDS <= "01010"; -- S7
            When 8 =>
                LEDS <= "10001"; -- S8

            When others => 
                LEDS <= "11111"; -- Restart Sequence
        End Case;               

    End Process;

Answer 1

这段代码非常好，但有一件事需要注意：

你不会同时拥有这两个包：

use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;

实际上，您的代码仅使用std_logic_unsigned包;它根本没有使用numeric_std包。 std_logic_unsigned包定义了std_logic_vector类型的各种算术运算符。这些假设无符号算术，因此名称。您正在使用此行中的std_logic_unsigned包：

Temp <= Temp + 1 ;

对于新代码，您应该使用numeric_std包，而不是std_logic_unsigned包。为此，您必须将Temp的类型更改为unsigned。类型unsigned只是std_logic的数组，如std_logic_vector，但顾名思义，它用于实现无符号算术。

所以，我会

i）删除这一行：

use ieee.std_logic_unsigned.all;

ii）更改此行：

SIGNAL Temp:   std_logic_vector (3 downto 0):= "0000"; -- initailise comparison signal

为：

SIGNAL Temp:   unsigned (3 downto 0):= "0000"; -- initailise comparison signal

iii）（正如Scary Jeff指出的那样）考虑Temp对"XXXX"的分配是做什么的。你不希望你的计数器回绕"0000"吗？如果您希望它冻结在"1000"，那么您需要一些不同的代码。在任何情况下，从不将任何代码放在测试之外的rising_edge时钟。（它不符合我向您展示的模板。您期望通过此代码生成什么逻辑？）

VHDL时钟LED序列第2部分

1 个答案: