Question

我正在尝试使用ISE 14.7生成一个编程文件，用于Trust-Hub.org上提供的一些基准测试。我正在使用AES-T100，其中包含一系列verilog文件。我从未与verilog合作过，多年来也没有接触过VHDL。

理论上，trust-hub提供的verilog代码应该可以正常工作，但尝试它会产生编译错误

ERROR:HDLCompilers:27 - "../../../../../../AES-T100/src/TjIn/TSC.v" line 28 Illegal redeclaration of 'load'

现在，这个错误是相当自我解释的，但是看一下初学者verilog教程here我可以看到完全相同的重复变量名称。

下面的verilog代码看起来是否正确或者在trust-hub代码中是否有错误？

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:20:01 03/06/2013 
// Design Name: 
// Module Name:    TSC 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module TSC(
    input rst,
    input clk,
    input [127:0] key,
    output [63:0] load
    );

    reg [63:0] load;
    wire [19: 0] counter;

    lfsr_counter lfsr (rst, clk, counter);
    always @ (posedge clk)
        begin
            load[0] <= key[0] ^ counter[0]; 
            load[1] <= key[0] ^ counter[0]; 
            load[2] <= key[0] ^ counter[0]; 
            load[3] <= key[0] ^ counter[0]; 
            load[4] <= key[0] ^ counter[0]; 
            load[5] <= key[0] ^ counter[0]; 
            load[6] <= key[0] ^ counter[0]; 
            load[7] <= key[0] ^ counter[0]; 

            load[8] <= key[1] ^ counter[1]; 
            load[9] <= key[1] ^ counter[1]; 
            load[10] <= key[1] ^ counter[1];    
            load[11] <= key[1] ^ counter[1];    
            load[12] <= key[1] ^ counter[1];    
            load[13] <= key[1] ^ counter[1];    
            load[14] <= key[1] ^ counter[1];    
            load[15] <= key[1] ^ counter[1];    

            load[16] <= key[2] ^ counter[2];    
            load[17] <= key[2] ^ counter[2];    
            load[18] <= key[2] ^ counter[2];    
            load[19] <= key[2] ^ counter[2];    
            load[20] <= key[2] ^ counter[2];    
            load[21] <= key[2] ^ counter[2];    
            load[22] <= key[2] ^ counter[2];    
            load[23] <= key[2] ^ counter[2];    

            load[24] <= key[3] ^ counter[3];    
            load[25] <= key[3] ^ counter[3];    
            load[26] <= key[3] ^ counter[3];    
            load[27] <= key[3] ^ counter[3];    
            load[28] <= key[3] ^ counter[3];    
            load[29] <= key[3] ^ counter[3];    
            load[30] <= key[3] ^ counter[3];                
            load[31] <= key[3] ^ counter[3];                

            load[32] <= key[4] ^ counter[4];    
            load[33] <= key[4] ^ counter[4];    
            load[34] <= key[4] ^ counter[4];    
            load[35] <= key[4] ^ counter[4];    
            load[36] <= key[4] ^ counter[4];    
            load[37] <= key[4] ^ counter[4];    
            load[38] <= key[4] ^ counter[4];    
            load[39] <= key[4] ^ counter[4];    

            load[40] <= key[5] ^ counter[5];    
            load[41] <= key[5] ^ counter[5];    
            load[42] <= key[5] ^ counter[5];    
            load[43] <= key[5] ^ counter[5];    
            load[44] <= key[5] ^ counter[5];    
            load[45] <= key[5] ^ counter[5];    
            load[46] <= key[5] ^ counter[5];                
            load[47] <= key[5] ^ counter[5];                

            load[48] <= key[6] ^ counter[6];    
            load[49] <= key[6] ^ counter[6];                
            load[50] <= key[6] ^ counter[6];    
            load[51] <= key[6] ^ counter[6];    
            load[52] <= key[6] ^ counter[6];    
            load[53] <= key[6] ^ counter[6];    
            load[54] <= key[6] ^ counter[6];    
            load[55] <= key[6] ^ counter[6];

            load[56] <= key[7] ^ counter[7];    
            load[57] <= key[7] ^ counter[7];    
            load[58] <= key[7] ^ counter[7];    
            load[59] <= key[7] ^ counter[7];    
            load[60] <= key[7] ^ counter[7];    
            load[61] <= key[7] ^ counter[7];    
            load[62] <= key[7] ^ counter[7];    
            load[63] <= key[7] ^ counter[7];                
        end

endmodule

修改我发现这个讨论here讨论了ansi样式标题。我将模块代码的顶部更改为：

module TSC(
    input rst,
    input clk,
    input [127:0] key,
     output reg [63:0] load
    );

    //reg [63:0] load;
    wire [19: 0] counter;

它有效。上面的样式是否不适用于较旧版本的verilog或其他东西？为什么他们会发布那些显然不起作用的“经过测试”的代码？

Answer 1

声明如下并删除reg [63:0] load;

//////////////////////////////////////////////////////////////
    module TSC(
    input rst,
    input clk,
    input [127:0] key,
    output reg[63:0] load
    );

Verilog：非法重新声明

1 个答案: