Question

大家好，我创造了一个Shift - 并 - 添加乘数。我很困惑为什么我的输出是错误的，总是在85.这是测试台的东西吗？顺便说一句，它正在发挥作用。

new1.v

`define M ACC[0]
module mult4X4 (Clk, St, Mplier, Mcand, Done, Result);

input Clk,St;
input [3:0] Mplier, Mcand;
output Done;
output [7:0] Result;

reg [3:0] State;
reg [8:0] ACC;

initial
begin
    State = 0;
    ACC = 0;
end

always @(posedge Clk)
begin
    case (State)
        0:
            begin
                if(St == 1'b1)
                begin
                    ACC[8:4] <= 5'b00000 ;
                    ACC[3:0] <= Mplier ;
                    State <= 1;
                end
            end
        1,3,5,7 :
            begin
                if(`M==1'b1)
                begin
                    ACC[8:4] <= {1'b0, ACC[7:4]} + Mcand ;
                    State <= State +1;
                end
                else
                begin
                    ACC <= {1'b0, ACC[8:1]};
                    State <= State + 2;
                end
            end
        2,4,6,8 :
            begin
                ACC <= {1'b0, ACC[8:1]};
                State <= State +1;
            end
        9:
            begin
                State <= 0;
            end
        endcase
    end

    assign Done = (State == 9) ? 1'b1 : 1'b0 ;
    assign Result = (State == 9) ? ACC[7:0] : 8'b01010101;
endmodule

tb_new1.v

module tb_mult4X4;
    reg Clk,St,nReset;
    reg [3:0] Mplier;
    reg [3:0] Mcand;
    wire Done;
    wire [7:0] Result;

    mult4X4 UUT (Clk,St,Mplier,Mcand,Done,Result);

    initial begin
        $dumpfile ("mult4X4.vpd");
        $dumpvars;
    end
    initial
        Clk = 0;

    always
        #5 Clk =~Clk;
    initial begin

        nReset = 0;
        St = 0; 
        Mcand = 4'b1101;
        Mplier = 4'b1011;

        #10
        nReset = 1;
        St = 1;
        Mcand = 4'b1111;
        Mplier = 4'b1001;

        #10

        Mcand = 4'b0101;
        Mplier = 4'b1010;

        #10

        Mcand = 4'b1111;
        Mplier = 4'b1111;

        #10
        Mcand = 4'b1101;
        Mplier = 4'b1010;

        $finish;
    end
endmodule

我跑了很多次代码，一切似乎跟着我的FSM。任何人都可以指出哪里出了问题。真的很困惑这个

Answer 1

#10是缩短的方法。您的RTL需要10个时钟才能完成，但您每个时钟都会更改输入（半个clk为#5）。使用#100或更好@(posedge Done);（这使得测试平台无论需要多少时钟都等待完成。）

用于移位和添加乘数的Verilog代码

1 个答案: