当我合成以下VHDL代码时，我得到了上述错误。
这是一种连接多个实体的顶级设计。
组件声明：
COMPONENT channel_memory IS
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0):= (OTHERS => '0');
addra : IN STD_LOGIC_VECTOR(11 DOWNTO 0):= (OTHERS => '0');
dina : IN STD_LOGIC_VECTOR(15 DOWNTO 0):= (OTHERS => '0');
douta : OUT STD_LOGIC_VECTOR(15 DOWNTO 0):= (OTHERS => '0')
);
END COMPONENT;
COMPONENT MAX5190 IS
PORT (
GCLK : IN STD_LOGIC; -- CLK in 200 MHz
RSTN : IN STD_LOGIC; -- Reset
OUTPUT_TRIGGER : IN STD_LOGIC; -- Enable the module (from controller)
TRIGGER_CHIRP : IN STD_LOGIC; -- Start chirping (from channel delay)
LOAD_ACK : IN STD_LOGIC; -- Data ready
DATA_LENGTH : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- Total words to send to DAC
DIN : IN STD_LOGIC_VECTOR (15 DOWNTO 0) := (OTHERS => '0'); -- Actual data to send to DAC
CHIRP_EN_TRIGGER : IN STD_LOGIC; -- Enable dac >> ××××××××××××
-- ×
-- Memory block ×
LOAD_OUTPUT : OUT STD_LOGIC; -- Request data ×
DATA_ADDR : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Adress to read from ×
-- ×
CHIRP_EN : OUT STD_LOGIC; -- opamp enable << ××××××××××
-- MAX5190 outputs
DAC_EN : OUT STD_LOGIC; -- DAC Enable (always high)
DAC_CS : OUT STD_LOGIC; -- DAC chip select
DAC_CLK : OUT STD_LOGIC; -- DAC clock out
DAC_DATA : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) := (OTHERS => '0') -- dac data
);
END COMPONENT;
COMPONENT memory_controll IS
PORT(
CLK : IN STD_LOGIC;
-- from controller
DATA_IN : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to store
DATA_LENGTH : in STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); -- number of words to store
RESET : IN STD_LOGIC; -- reset module
NEW_DATA : IN STD_LOGIC; -- new data available flag
WRITE_ENABLE : IN STD_LOGIC; -- enable writing
-- from MAX5190
ADDRESS_SELECT : IN STD_LOGIC_VECTOR ( 11 DOWNTO 0 ) := (others => '0'); -- addres selected by MAX5190 driver
REQUEST_DATA : IN STD_LOGIC; -- request data
DATA_OUT : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to MAX5190 driver
DATA_READY : OUT STD_LOGIC; -- data to MAX5190 driver ready
-- to memory
DOUTA : IN STD_LOGIC_VECTOR ( 15 DOWNTO 0 ) := (others => '0'); -- data from memory
DINA : OUT STD_LOGIC_VECTOR ( 15 DOWNTO 0 ); -- data to memory
ADDRA : OUT STD_LOGIC_VECTOR ( 11 DOWNTO 0 ); -- addres to write or read
WEA : OUT STD_LOGIC_VECTOR ( 0 DOWNTO 0); -- write enable
RSTA : OUT STD_LOGIC -- reset memory
);
端口映射：
gen: for i in 1 to number_of_channels generate
-- memory controll
memcont: memory_controll
PORT MAP(
CLK => clk400MHz,
-- from controller
DATA_IN => MEMORY_CONTROL_DATA,
DATA_LENGTH => MEMORY_CONTROL_DATA_LENGTH,
RESET => BUTTON,
NEW_DATA => MEMORY_CONTROL_NEW_DATA,
WRITE_ENABLE => MEMORY_CONTROL_WRITE_ENABLE,
-- from MAX5190
ADDRESS_SELECT => ADDRESS_SELECT (i),
REQUEST_DATA => REQUEST_DATA (i),
DATA_OUT => DATA_OUT (i),
DATA_READY => DATA_READY (i),
-- to memory
DOUTA => DOUTA (i),
DINA => DINA (i),
ADDRA => ADDRA (i),
WEA => WEA (i),
RSTA => RSTA (i)
);
-- max5190
max: max5190
PORT MAP(
GCLK => clk200MHz,
RSTN => MAX5190_RESET,
OUTPUT_TRIGGER => MAX5190_ENABLE,
TRIGGER_CHIRP => TRIGGER_CHIRP (i),
LOAD_ACK => DATA_READY (i),
DATA_LENGTH => MAX5190_DATA_LENGTH,
DIN => DATA_OUT (i),
CHIRP_EN_TRIGGER => MAX5190_CHIRP_ENABLE,
-- Memory block
LOAD_OUTPUT => REQUEST_DATA (i),
DATA_ADDR => ADDRESS_SELECT (i),
CHIRP_EN => CHIRP_EN (i),
-- MAX5190 outputs
DAC_EN => DAC_EN (i),
DAC_CS => DAC_CS (i),
DAC_CLK => CHANNEL_CLKS (i),
DAC_DATA => CHANNELS (i)
);
-- memory
mem: channel_memory
PORT MAP(
clka => clk400MHz,
rsta => BUTTON,
wea => WEA (i),
addra => ADDRA (i),
dina => DINA (i),
douta => DOUTA (i)
);
我声明我的类型的包：
PACKAGE jelle IS
FUNCTION lookup (input: STD_LOGIC_VECTOR(15 DOWNTO 0)) RETURN INTEGER;
FUNCTION jOR (input: STD_LOGIC_VECTOR( 7 DOWNTO 0)) RETURN STD_LOGIC;
TYPE VECTOR_ARRAY is array (POSITIVE) of STD_LOGIC_VECTOR( 7 downto 0);
TYPE ADDRESS_ARRAY is array (POSITIVE) of STD_LOGIC_VECTOR(11 downto 0);
TYPE DATA_ARRAY is array (POSITIVE) of STD_LOGIC_VECTOR(15 downto 0);
TYPE WEA_ARRAY is array (POSITIVE) of STD_LOGIC_VECTOR( 0 downto 0);
END PACKAGE;
上一次我合成代码这些警告，现在他们已经改为错误，但我认为它们仍然非常重要。
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 288: Output port <CLK_OUT3> of the instance <dcm> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 288: Output port <LOCKED> of the instance <dcm> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 296: Output port <MAX5190_CHIRP_ENABLE_TRIGGER> of the instance <contr> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port <DATA_OUT> of the instance <gen[1].memcont> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port <DINA> of the instance <gen[1].memcont> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port <ADDRA> of the instance <gen[1].memcont> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port <WEA> of the instance <gen[1].memcont> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 365: Output port <RSTA> of the instance <gen[1].memcont> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 391: Output port <DATA_ADDR> of the instance <gen[1].max> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 391: Output port <DAC_DATA> of the instance <gen[1].max> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "E:\Projects\VHDL\New_Phase\toplevel.vhd" line 414: Output port <douta> of the instance <gen[1].mem> is unconnected or connected to loadless signal.
这些错误会为每个生成的对象重复这些错误。 输入端口被赋予默认值，因为编译器一直要求它有错误（不知道为什么）。
如果有人能帮助我那太棒了!!
答案 0 :(得分：0)
简单地不使用连接到实例化模块的信号，因此例如实例＆lt; gen [1] .memcont＆gt;的输出端口＆lt; DATA_OUT＆gt;消息未连接或连接到无负载信号“。
因此，看看实例化组件的模块，或上面的模块，连接实例化模块的输出，因为输出可能在那里使用; - ）