固定时钟发生器，带有名为num_cycles的通用参数

Question

我必须让它显示与num_cycle变量一样多的脉冲。因此，如果设置为3，则会有3个时钟脉冲。我已经走到了这一步：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fixed_clock is
    generic ( num_cycles : integer := 1); --at least 1
    Port ( enable : in STD_LOGIC;
           reset : in STD_LOGIC;
           clk_out : inout STD_LOGIC);
end fixed_clock;

architecture Behavioral of fixed_clock is
begin
    process(enable, reset)
    begin
        if(reset='1') then
            clk_out<='0';
        elsif(enable='1') then
            for I in 1 to num_cycles*2 loop
                 clk_out<=not clk_out;
            end loop;
        end if;
    end process;
end Behavioral;

我也写了测试台

library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity fixed_clock_tb is
end;

architecture bench of fixed_clock_tb is

  component fixed_clock
      generic ( num_cycles : integer := 1);
      Port ( enable : in STD_LOGIC;
             reset : in STD_LOGIC;
             clk : inout STD_LOGIC);
  end component;

  signal enable: STD_LOGIC;
  signal reset: STD_LOGIC;
  signal clk: STD_LOGIC;
  signal num_cycles: INTEGER;
begin

  -- Insert values for generic parameters !!
  uut: fixed_clock generic map ( num_cycles =>  num_cycles)
                      port map ( enable     => enable,
                                 reset      => reset,
                                 clk        => clk );

  stimulus: process
  begin

    num_cycles:=3;
    enable<=0;
    reset<='1';
    wait for 10 ns;
    reset<='0';
    enable<='1';
    wait for 50 ns;

    wait;
  end process;
end;

我一直收到错误。我该怎么办？