如何将此systemverilog代码转换为可合成的systemverliog或vhdl或verlog

Question

module lookup_table_unq1
(
    input logic [7:0]     curr_state,
    input logic [31:0]    lookup_data,

    output logic [7:0]     nxt_state,
    output logic [4:0]     rd_amt,
    output logic [1:0][3:0] rd_offset,

    output logic [3:0][3:0] ev_src,
    output logic [3:0][5:0]   ev_dst,
    output logic [2:0]         found_hdr,
    output logic [2:0][4:0]  found_hdr_type,
    output logic [2:0][3:0]  found_hdr_pos,
    output logic [2:0][7:0]  found_hdr_size,

    // Global Signals
    input logic                 clk,
    input logic                 rst
);

always_comb
begin
    ev_src[0] = '1; ev_dst[0] = '1;    
    ev_src[1] = '1; ev_dst[1] = '1;    
    ev_src[2] = '1; ev_dst[2] = '1;    
    ev_src[3] = '1; ev_dst[3] = '1;    
    found_hdr = '0;
    found_hdr_type[0] = '0;
    found_hdr_pos[0] = '0;
    found_hdr_size[0] = '0;
    found_hdr[1] = '0;
    found_hdr_type[1] = '0;
    found_hdr_pos[1] = '0;
    found_hdr_size[1] = '0;
    found_hdr[2] = '0;
    found_hdr_type[2] = '0;
    found_hdr_pos[2] = '0;
    found_hdr_size[2] = '0;

    casex ({curr_state, lookup_data})
        {8'b_0101_0010, 16'b_0000_1000_0000_0000, 16'b_????_????_????_????} : begin
            nxt_state = curr_state & ~8'd255 |
                        8'd73 & 8'd255;
            rd_amt = 5'd8;
            rd_offset[0] = 4'd0;
            rd_offset[1] = 4'd0;
            ev_src[0] = 4'd4; ev_dst[0] = 6'd14;
            ev_src[1] = 4'd5; ev_dst[1] = 6'd15;
            ev_src[2] = 4'd6; ev_dst[2] = 6'd3;
            ev_src[3] = 4'd7; ev_dst[3] = 6'd4;
            found_hdr[0] = 1'd1;found_hdr_type[0] = 5'd6; found_hdr_pos[0] = 4'd6; found_hdr_size[0] = 8'd20;
            found_hdr[1] = 1'd0; found_hdr_type[1] = 5'd0; found_hdr_pos[1] = 4'd0; found_hdr_size[1] = 8'd0;
            found_hdr[2] = 1'd0; found_hdr_type[2] = 5'd0; found_hdr_pos[2] = 4'd0; found_hdr_size[2] = 8'd0;
        end

        {8'b_0101_0010, 16'b_????_????_????_????, 16'b_????_????_????_????} : begin
            nxt_state = curr_state & ~8'd255 |
                        8'd255 & 8'd255;
            rd_amt = 5'd6;
            rd_offset[0] = 4'd0;
            rd_offset[1] = 4'd0;
            ev_src[0] = 4'd4; ev_dst[0] = 6'd14;
            ev_src[1] = 4'd5; ev_dst[1] = 6'd15;
            ev_src[2] = 4'd0; ev_dst[2] = -6'd1;
            ev_src[3] = 4'd0; ev_dst[3] = -6'd1;
            found_hdr[0] = 1'd0;found_hdr_type[0] = 5'd0; found_hdr_pos[0] = 4'd0; found_hdr_size[0] = 8'd0;
            found_hdr[1] = 1'd0; found_hdr_type[1] = 5'd0; found_hdr_pos[1] = 4'd0; found_hdr_size[1] = 8'd0;
            found_hdr[2] = 1'd0; found_hdr_type[2] = 5'd0; found_hdr_pos[2] = 4'd0; found_hdr_size[2] = 8'd0;
        end


        default : begin
           nxt_state = 8'd255;
            rd_amt = 5'd16;
         rd_offset[0] = 4'd0;
           rd_offset[1] = 4'd0;
            ev_src[0] = 4'd15; ev_dst[0] = 6'd63;
            ev_src[1] = 4'd15; ev_dst[1] = 6'd63;
            ev_src[2] = 4'd15; ev_dst[2] = 6'd63;
            ev_src[3] = 4'd15; ev_dst[3] = 6'd63;
        end
    endcase
end

endmodule : lookup_table_unq1