我正在尝试构建一个C ++应用程序，该应用程序调用Xilinx ISE（sch2vhdl，xst，ngdbuild等）附带的命令行工具来自动执行一系列构建。只有在应用程序调用时，应用程序才会遇到其中一个工具（xst）抛出的错误，这使我认为这是C ++的权限问题，而不是来自Xilinx的任何问题。
C ++应用程序背后的想法是使用System（）函数来准确地与命令提示符进行交互。我能够使用这些相同的命令从Windows命令提示符执行合成，从而证明我的方法是可行的。但是，当我从应用程序调用xst工具时，该工具已成功调用并运行但失败并显示“无写入访问”错误。当我将其复制并粘贴到命令行但使用System（）函数失败时，确切的语句非常有效。
对于那些熟悉Xilinx的人，我只需要调用这两个命令：
sch2hdl -batch C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/sch2HdlBatchFile
xst -ifn C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.xst -ofn C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.syr
同样，当我从cmd调用它们时，它们都是成功的。第二个，当C ++应用程序使用完全相同的语句时，XST失败。
失败的地方：xst工具创建一个包含三个子文件夹的文件夹'xst'。然后在子文件夹中填充重要文件，以便我需要调用下一个命令（还没有到达那里）。当应用程序运行时，它使用上面的命令调用xst并收到以下错误：
ERROR:Xst:439 - No write access in xst/projnav.tmp
这只是猜测，但出于安全原因，可能由C ++调用的任何程序都具有有限的写入能力。如果是这样的话有什么办法可以改变吗？除此之外我没有想法。
以下是我目前正在处理的C ++代码以供澄清
#include "stdafx.h"
#include <stdio.h>
#include <stdlib.h>
#include <iostream>
#include <fstream>
#include <sddl.h>
#include <windows.h>
void convertSchematicToHDL() {
printf("Executing sch2hdl\n");
//Call first command line tool
system("sch2hdl -batch C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/sch2HdlBatchFile");
}
void callXST() {
printf("\n\nExecuting Synthesis\n");
//Create the necessary subfiles for xst to populate
std::string outputFolder = "C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/xst";
CreateDirectoryA(outputFolder.c_str(), NULL);
outputFolder = "C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/xst/projnav.tmp";
CreateDirectoryA(outputFolder.c_str(), NULL);
//===========================================================//
//This is the line that fails
system("xst -ifn C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.xst -ofn C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.syr");
}
//Create configuration files needed by xst
void makeInitFiles() {
std::ofstream prjFile;
prjFile.open("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.prj");
prjFile << "vhdl work \"item.vhf\"";
prjFile.close();
std::ofstream syrFile;
syrFile.open("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.syr");
syrFile.close();
std::ofstream xstFile;
xstFile.open("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.xst");
xstFile << "set -tmpdir \"xst/projnav.tmp\"\n";
xstFile << "set -xsthdpdir \"xst\"\n";
xstFile << "run\n";
xstFile << "-ifn item.prj\n";
xstFile << "-ifmt mixed\n";
xstFile << "-ofn item\n";
xstFile << "-ofmt NGC\n";
xstFile << "-p xa3s100e-4-vqg100\n";
xstFile << "-top item\n";
xstFile << "-opt_mode Speed\n";
xstFile << "-opt_level 1\n";
xstFile << "-iuc NO\n";
xstFile << "-keep_hierarchy No\n";
xstFile << "-netlist_hierarchy As_Optimized\n";
xstFile << "-rtlview Yes\n";
xstFile << "-glob_opt AllClockNets\n";
xstFile << "-read_cores YES\n";
xstFile << "-write_timing_constraints NO\n";
xstFile << "-cross_clock_analysis NO\n";
xstFile << "-hierarchy_separator /\n";
xstFile << "-bus_delimiter <>\n";
xstFile << "-case Maintain\n";
xstFile << "-slice_utilization_ratio 100\n";
xstFile << "-bram_utilization_ratio 100\n";
xstFile << "-verilog2001 YES\n";
xstFile << "-fsm_extract YES -fsm_encoding Auto\n";
xstFile << "-safe_implementation No\n";
xstFile << "-fsm_style LUT\n";
xstFile << "-ram_extract Yes\n";
xstFile << "-ram_style Auto\n";
xstFile << "-rom_extract Yes\n";
xstFile << "-mux_style Auto\n";
xstFile << "-decoder_extract YES\n";
xstFile << "-priority_extract Yes\n";
xstFile << "-shreg_extract YES\n";
xstFile << "-shift_extract YES\n";
xstFile << "-xor_collapse YES\n";
xstFile << "-rom_style Auto\n";
xstFile << "-auto_bram_packing NO\n";
xstFile << "-mux_extract Yes\n";
xstFile << "-resource_sharing YES\n";
xstFile << "-async_to_sync NO\n";
xstFile << "-mult_style Auto\n";
xstFile << "-iobuf YES\n";
xstFile << "-max_fanout 100000\n";
xstFile << "-bufg 24\n";
xstFile << "-register_duplication YES\n";
xstFile << "-register_balancing No\n";
xstFile << "-slice_packing YES\n";
xstFile << "-optimize_primitives NO\n";
xstFile << "-use_clock_enable Yes\n";
xstFile << "-use_sync_set Yes\n";
xstFile << "-use_sync_reset Yes\n";
xstFile << "-iob Auto\n";
xstFile << "-equivalent_register_removal YES\n";
xstFile << "-slice_utilization_ratio_maxmargin 5\n";
xstFile.close();
}
//Cleanup
void deleteFiles() {
std::remove("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.prj");
std::remove("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.syr");
std::remove("C:/Users/Nick/Documents/XilinxProjects/SingleItemTest/item.xst");
}
int main()
{
printf("Checking if processor is available...");
if (system(NULL)) puts("Ok");
else exit(EXIT_FAILURE);
deleteFiles();
makeInitFiles();
convertSchematicToHDL();
callXST();
return 0;
}
C ++应用程序调用时XST函数的输出
Release 14.7 - xst P.20131013 (nt)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.08 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.09 secs
-->
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "item.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "item"
Output Format : NGC
Target Device : xa3s100e-4-vqg100
---- Source Options
Top Module Name : item
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
ERROR:Xst:439 - No write access in xst/projnav.tmp\
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.40 secs
-->
Total memory usage is 239576 kilobytes
Number of errors : 1 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)