新秀测试助手，不能做出错误的头或尾。 （使用Icarus Verilog）

Question

我一直试图让这个代码突然出现。在大多数情况下，我认为我确定模块本身没问题。它的测试平台摒弃了所有的错误。

这里是完整的代码：

/*
Primitive code to control a stepper motor using FPGA
It will run as a seconds hand
9 June 2016
dwiref024
*/

module clock_divider(clock, reset, clock_div);

input clock;
input reset;

output clock_div;
reg [25:0]counter = 26'd0;

// Assuming a clock frequency of 40Mhz
// log2(40M) = 25.25
// Therefore 40MHz corresponds to MOD25
always@(posedge clock, negedge reset)   begin
    if(!reset) begin
        counter <= 26'd0;   
    end

    if(counter == 26'd40000000) begin
        counter <= 26'd0;
    end

    else begin
    counter <= counter + 1;
    end

end

assign clock_div = counter[24]; // Gives you a clock signal 'clock_div'of approximate frequency 1Hz

initial begin
    $dumpvars(0, clock, reset, counter);
end
endmodule

module count_seconds (
input clock_div, reset
);
reg [5:0]seconds = 6'd0;

always@(posedge clock_div, negedge reset) begin
    if (!reset) begin
        seconds <= 0;
    end
    else if (seconds == 6'd60) begin
        seconds <= 0;
    end

    else begin
        seconds <= seconds + 1;
    end
end
initial begin
    $dumpvars (0, clock_div, seconds);
end

endmodule

module get_servo(
input clock_div,
output reg servoPin = 0, 
output reg ding
);

always@(posedge clock_div)  begin
    if(clock_div)
        ding <= 1;
    else
        ding <= 0;
end
always@(ding)   begin

    if (ding) begin
        servoPin = 1'b1;
    end
    else servoPin = 1'b0;
end


initial begin
    $dumpvars (0, servoPin);
end

endmodule

module clk_tb;
reg clock;
reg reset;
reg servoPin;
reg clock_div;
reg ding;
initial begin
    clock = 0;
    reset = 0;  
    repeat(2) #10 clock = ~clock;
    reset = 1;
    forever #10 clock = ~clock; 
end

clock_divider DUT1 (clock, reset, clock_div);
get_servo DUT2 (clock_div, servoPin, ding);

initial begin
    servoPin = 1'b1;
    #1 clock_div = 1'b0;
    $finish;
end

endmodule

运行

$ icarusverilog -o servo servo.v

我收到以下错误：

servo.v:105: error: reg clock_div; cannot be driven by primitives or continuous assignment.
servo.v:105: error: Output port expression must support continuous assignment.
servo.v:105:      : Port 3 (clock_div) of clock_divider is connected to clock_div
servo.v:106: error: reg servoPin; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106:      : Port 2 (servoPin) of get_servo is connected to servoPin
servo.v:106: error: reg ding; cannot be driven by primitives or continuous assignment.
servo.v:106: error: Output port expression must support continuous assignment.
servo.v:106:      : Port 3 (ding) of get_servo is connected to ding
6 error(s) during elaboration.

我在这里看了看板，看到了在测试台模块中使用reg的时间和地点的问题，以避免这个问题：

<variable name> is not a valid l-value in foo

这是我得到的第一批错误之一。为了避免它，我最终得到了这些。 如果有人能够指出这些错误的根本原因以及它们的来源，我可能能够解决这个问题并在此过程中学习新的东西。

Answer 1

信号clock_div，servoPin由多个驱动程序驱动。您已将servoPin作为get_servo模块和测试平台clk_tb本身的输出驱动。这是非法的。

关于clock_div，请参阅下图：

模块的输出必须连接到电线。这里，clock_div是clock_divider模块的输出端口，必须是有线类型。然后，该输出线可以用作驱动servoPin模块的逻辑输入。以下是测试平台代码中的代码段：

reg clock;
reg reset;
reg servoPin;
// reg clock_div; // remove this
wire clock_div_w, clock_div_w2;
assign clock_div_w2 = clock_div_w; // drive output from one module to input to another
//...
clock_divider DUT1 (clock, reset, clock_div_w); // wire output
get_servo DUT2 (clock_div_w2, servoPin, ding);  // another wire input
//...
initial begin
    // servoPin = 1'b1; // donot drive from here, module output
    #1 clock_div = 1'b0;
    $finish;
end

类似的评论适用于ding端口。

参考IEEE 1800-2012，第23.3.3节：

  

每个端口连接应为源的连续分配   下沉，其中一个连接项应为信号源，另一个为连接项   应该是信号汇。任务应是连续的   输入或输出端口从源到接收器的分配。

当端口以实例化连接到任何其他端口时，它是常量分配，因此它始终需要目标端口网。

有关详细信息，请参阅Port connection rules question。