Question

Quartus2V13.0SP1 DE1board VHDL

我是大学生。

教授说＆＃34;不要使用CLOCK和＆＃39;事件＆＃34;。

昨天我在7segmentLED上做了反向开球。

我今天编辑了很多这样的问题。

Code1以下是正确的行为。

我希望在没有＆＃34;＆＃39;事件＆＃34;的情况下在Code2上执行此操作。

--Code1
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;

entity increase is
    port(
        key0 : in std_logic;
        hex3 : out std_logic_vector(6 downto 0));
end increase;

architecture RTL of increase is
    signal hex3c : integer range 0 to 9;
    begin
        process(key0, hex3c)begin
            if(key0' event and key0 = '0') then
                if(hex3c = 9) then 
                    hex3c <= 0;    
                else        
                    hex3c <= hex3c + 1;             
                end if;
            end if;
        end process;        
    process(hex3c)
    begin   
    case hex3c is
        when 0 => hex3 <= "1000000";
        when 1 => hex3 <= "1111001";
        when 2 => hex3 <= "0100100";
        when 3 => hex3 <= "0110000";
        when 4 => hex3 <= "0011001";
        when 5 => hex3 <= "0010010";
        when 6 => hex3 <= "0000010";
        when 7 => hex3 <= "1111000";
        when 8 => hex3 <= "0000000";
        when others => hex3 <= "0010000";
        end case;
    end process;
end RTL;

和

--Code2
library IEEE;
use ieee.std_logic_1164.all ;
use IEEE.std_logic_unsigned.all;

entity increase is
    port(
        key0 : in std_logic;
        hex3 : out std_logic_vector(6 downto 0));
end increase;

architecture RTL of increase is
    signal hex3c : integer range 0 to 9;
    signal prev : std_logic;
    begin
        process(key0, hex3c, prev)begin
            if(key0 = '0' and prev = '0')then
                if(hex3c = 9) then 
                    hex3c <= 0;
                    prev <= '1';
                else        
                    hex3c <= hex3c + 1;
                    prev <= '1';
                end if;
            elsif(key0 = '1' and prev = '1')then
                prev <= '0';
            end if;
        end process;        
    process(hex3c)
    begin   
    case hex3c is
        when 0 => hex3 <= "1000000";
        when 1 => hex3 <= "1111001";
        when 2 => hex3 <= "0100100";
        when 3 => hex3 <= "0110000";
        when 4 => hex3 <= "0011001";
        when 5 => hex3 <= "0010010";
        when 6 => hex3 <= "0000010";
        when 7 => hex3 <= "1111000";
        when 8 => hex3 <= "0000000";
        when others => hex3 <= "0010000";
        end case;
    end process;
end RTL;

请告诉我如何解决这个问题。

我们真的能意识到这一点吗？

Answer 1

我现在附近没有评估板来测试你的代码，但现在唯一可能是问题的是你的敏感度列表。尝试将count放入其中，以便在其更改时随时更新。

我能给你的另一个建议是把每一个可能的情况 - 即。使用组合过程时，在您的过程中添加else语句。

现在让我改变一切。

Answer 2

所以你想要一个异步计数器，或者你正在寻找rising_edge（时钟）而不是if（时钟=＆＃39; 1＆＃39;和时钟＆＃39;事件）呢？

VHDL，FPGA，7段LED带按钮

2 个答案: