Question

我有一个项目来创建一个带有时钟和复位信号的ALU，但是对于下面的代码，这个错误会出现＆＃34;非法顺序语句＆＃34;。我认为问题是在进程内实例化实体。我该如何解决这个问题？

library ieee;
use ieee.std_logic_1164.all;

entity alu is
    port(a: in std_logic_vector(31 downto 0);
         b: in std_logic_vector(31 downto 0);
         c: in std_logic_vector(31 downto 0);
         opcode: in std_logic_vector(2 downto 0);
         rst: in std_logic;      
         cout: out std_logic;
         output: out std_logic_vector(31 downto 0);
         zero: out std_logic);
end alu;

architecture my_arch of alu is

    component mux4to1_32bits
    port (and_in: in std_logic_vector(31 downto 0);
          not_in: in std_logic_vector(31 downto 0);
              or_in: in std_logic_vector(31 downto 0);
          xor_in: in std_logic_vector(31 downto 0);
          sel: in std_logic_vector(1 downto 0);
              f: out std_logic_vector(31 downto 0));
    end component;

    component mux2to1_32bits 
    port (in1: in std_logic_vector(31 downto 0);
          in2: in std_logic_vector(31 downto 0);
          sel: in std_logic;
          output: out std_logic_vector(31 downto 0));
    end component;

    component full_adder_32bits
    port (in_a: in std_logic_vector(31 downto 0);
          in_b: in std_logic_vector(31 downto 0);
          cin: in std_logic;
          fa: out std_logic_vector(31 downto 0);
          cout: out std_logic);
    end component;

    component and_32bits
    port (in1: in std_logic_vector(31 downto 0);
          in2: in std_logic_vector(31 downto 0);
          output: out std_logic_vector(31 downto 0));
    end component;

    component or_32bits
    port (in1: in std_logic_vector(31 downto 0);
          in2: in std_logic_vector(31 downto 0);
          output: out std_logic_vector(31 downto 0));
    end component;

    component not_32bits
    port (in1: in std_logic_vector(31 downto 0);
          output: out std_logic_vector(31 downto 0));
    end component;

    component xor_32bits
    port (in1: in std_logic_vector(31 downto 0);
          in2: in std_logic_vector(31 downto 0);
          output: out std_logic_vector(31 downto 0));
    end component;

    component zero_flag
    port ( result: in std_logic_vector(31 downto 0);
           zf: out std_logic);
    end component;

    signal port_and: std_logic_vector(31 downto 0);
    signal port_or: std_logic_vector(31 downto 0);
    signal port_not: std_logic_vector(31 downto 0);
    signal port_xor: std_logic_vector(31 downto 0);

    signal port_not1: std_logic_vector(31 downto 0);
    signal output_mux2to1: std_logic_vector(31 downto 0);
    signal output_mux4to1: std_logic_vector(31 downto 0);
    signal output_fa: std_logic_vector(31 downto 0);
    signal mid_output: std_logic_vector(31 downto 0);

    signal Clk : std_logic := '0';
    constant Clk_period : time := 10 ns;

begin
    Clk_process :process
    begin
            Clk <= '0';
            wait for Clk_period/2;
            Clk <= '1';
            wait for Clk_period/2;
    end process;

    stim_proc: process
    begin     
        wait for Clk_period*2;
        and_port: and_32bits port map (a(31 downto 0),b(31 downto 0),port_and(31 downto 0));
        not_port: not_32bits port map (a(31 downto 0),port_not(31 downto 0));
        or_port:  or_32bits port map (a(31 downto 0),b(31 downto 0),port_or(31 downto 0));
        xor_port: xor_32bits port map (a(31 downto 0),b(31 downto 0),port_xor(31 downto 0));
        not1_port: not_32bits port map (b(31 downto 0),port_not1(31 downto 0));

        mux2to1_1: mux2to1_32bits port map (b(31 downto 0),port_not1(31 downto 0),opcode(0),output_mux2to1(31 downto 0));
        mux4to1: mux4to1_32bits port map (port_and(31 downto 0),port_not(31 downto 0),port_or(31 downto 0),port_xor(31 downto 0),opcode(1 downto 0),output_mux4to1(31 downto 0));
        fulladder: full_adder_32bits port map (a(31 downto 0),output_mux2to1(31 downto 0),opcode(0),output_fa(31 downto 0),cout);
        mux2to1_2: mux2to1_32bits port map (output_fa(31 downto 0),output_mux4to1(31 downto 0),opcode(2),mid_output(31 downto 0));
        zero_output: zero_flag port map (mid_output(31 downto 0),zero);

        output <= mid_output;
        wait;

    end process;
end my_arch;

Answer 1

你是对的。您应该在stim_proc之外实例化组件的端口映射。可以想象或将其可视化为在旁边，或在旁边。它只是组件和过程电路之间信号的接线。在此过程中，您将只拥有描述数据如何通过在您的流程和组件之间运行的信号的代码。

Alu与时钟和重置

1 个答案: