我正在尝试使用条件求和加法器制作一个8位顺序乘法器，并且我的rtl模拟工作完全正常，但是网表模拟生成垃圾值并且报告中没有错误。唯一可疑的是有关生成的时序循环和许多警告的信息，如
Disabling timing arc between pins 'A' and 'Z' on cell 'U90'
to break a timing loop. (OPT-314)
我不知道该怎么办!!! 提前谢谢。
设计模块：
`timescale 1ns / 10ps
module sm8bittry (reset,clock,start,mlier,mcand,prodt,valid);
parameter w=8;
input clock,reset,start;
input [w-1:0] mlier,mcand;
reg [w-1:0] a1,b1;
output reg [w*2-1:0] prodt;
output reg valid;
reg os1;
reg [2:0] pstate, nstate;
integer i=0;
parameter s0=3'b000, s1=3'b001, s2=3'b010, s17=3'b011,s11=3'b111;
reg [2*w:0] ACC;
wire M;
assign M = ACC[0];
wire [w:0] accum;
csa1 c1(a1,b1,accum);
always @(posedge clock)
begin
if (reset==1)i<=0; else if(os1==1)i<=i; else i<=i+1;
if(start==1 & reset==0) pstate <= s0;
else pstate <= nstate;
end
always @(pstate) //Output (Action)
begin
case (pstate)
s1: begin
if (reset==1)
begin ACC<=16'b0; prodt<=0; valid<=1'b0; a1<=0; b1<=0; end
else begin ACC<=ACC; prodt<=0; valid<=1'b0; a1<=mcand; b1<={ACC[2*w-1:w]}; end
end
s0:begin
a1<=0;b1<=0;
if (reset==1)
begin ACC<=16'b0; prodt <=0; valid<=1'b0; end
else begin ACC[2*w:w] <= 9'b0; ACC[w-1:0] <= mlier; prodt <=0; valid<=1'b0; end
end
s17:begin
a1<=0;b1<=0;
if(reset==1)
begin ACC<=16'b0; valid<=1'b0; prodt<=0; end
else begin ACC<=ACC; valid<=1'b1; prodt <= ACC[w*2-1:0]; end
end
s11:begin
a1<=0;b1<=0;
if (reset==1)
begin ACC<=16'b0; prodt<=0; valid<=1'b0; end
else begin ACC<={accum,ACC[w-1:0]}>>1; prodt<=0; valid<=1'b0; end
end
s2:begin
a1<=0;b1<=0;
if (reset==1)
begin ACC<=16'b0; prodt <=0; valid<=1'b0; end
else begin ACC<=ACC>>1; prodt <=0; valid<=1'b0; end
end
default:begin a1<=0;b1<=0;valid<=1'b0;prodt <=0;ACC<=ACC;end
endcase
end
always @(*)
begin
case (pstate)
s0: begin os1<=0; if (i<w+1) begin if(M) nstate <= s1; else nstate <= s2; end else nstate<=s17; end
s11: begin os1<=0; if (i<w+1) begin if(M) nstate <= s1; else nstate <= s2; end else nstate<=s17; end
s2: begin os1<=0; if (i<w+1) begin if(M) nstate <= s1; else nstate <= s2; end else nstate<=s17; end
s1: begin os1<=1; nstate <= s11; end
s17: begin os1<=0; nstate<=s17; end
default: begin os1<=0; nstate<=s0; end
endcase
end
endmodule
// Module for 8-bit conditional sum adder
module csa1(a,b/*,cin,sum,cout*/,acc);
parameter W=8;
// Inputs declarations
input [W-1:0] a, b; // Two inputs a and b with a carry in cin
output [W:0] acc;
reg cin=0;//input cin;
// Outputs declarations
/*output */reg [W-1:0] sum; // Sum and carry cout
/*output */reg cout;
// Intermediate wires
wire s1_0, c2_0, s2_0, c3_0, s3_0, c4_0, s4_0, c5_0, s5_0, c6_0, s6_0,c7_0, s7_0, c8_0;
wire s2_1, c3_1;
wire s1_1, c2_1,s3_1, c4_1, s4_1, c5_1, s5_1, c6_1, s6_1, c7_1,s7_1, c8_1;
// Intermediate registers
reg fcout;
reg s3_level_1_0, s3_level_1_1, s5_level_1_0, s5_level_1_1, s7_level_1_0,s7_level_1_1;
reg c4_level_1_0, c4_level_1_1, c6_level_1_0, c6_level_1_1, c8_level_1_0,c8_level_1_1;
reg c2_level_1;
reg c4_level_2;
reg s6_level_2_0, s6_level_2_1, s7_level_2_0, s7_level_2_1, c8_level_2_0,c8_level_2_1;
// Level 0
always @(*)
{fcout,sum[0]}=a[0]+b[0]+cin;
// Conditional cells instantiation
conditional_cell c1( a[1], b[1], s1_0, s1_1, c2_0, c2_1);
conditional_cell c2( a[2], b[2], s2_0, s2_1, c3_0, c3_1);
conditional_cell c3( a[3], b[3], s3_0, s3_1, c4_0, c4_1);
conditional_cell c4( a[4], b[4], s4_0, s4_1, c5_0, c5_1);
conditional_cell c5( a[5], b[5], s5_0, s5_1, c6_0, c6_1);
conditional_cell c6( a[6], b[6], s6_0, s6_1, c7_0, c7_1);
conditional_cell c7( a[7], b[7], s7_0, s7_1, c8_0, c8_1);
assign acc={cout,sum};
// Level 1 muxes
always @*
case(fcout) // For first mux
1'b0:{c2_level_1,sum[1]}={c2_0,s1_0};
1'b1:{c2_level_1,sum[1]}={c2_1,s1_1};
endcase
always @* // For 2nd mux
case(c3_0)
1'b0: {c4_level_1_0, s3_level_1_0}={c4_0, s3_0};
1'b1: {c4_level_1_0, s3_level_1_0}={c4_1, s3_1};
endcase
always @* // For 3rd mux
case(c3_1)
1'b0: {c4_level_1_1, s3_level_1_1}={c4_0, s3_0};
1'b1: {c4_level_1_1, s3_level_1_1}={c4_1, s3_1};
endcase
always @* // For 4th mux
case(c5_0)
1'b0: {c6_level_1_0, s5_level_1_0}={c6_0, s5_0};
1'b1: {c6_level_1_0, s5_level_1_0}={c6_1, s5_1};
endcase
always @* // For 5th mux
case(c5_1)
1'b0: {c6_level_1_1, s5_level_1_1}={c6_0, s5_0};
1'b1: {c6_level_1_1, s5_level_1_1}={c6_1, s5_1};
endcase
always @* // For 6th mux
case(c7_0)
1'b0: {c8_level_1_0, s7_level_1_0}={c8_0, s7_0};
1'b1: {c8_level_1_0, s7_level_1_0}={c8_1, s7_1};
endcase
always @* // For 7th mux
case(c7_1)
1'b0: {c8_level_1_1, s7_level_1_1}={c8_0, s7_0};
1'b1: {c8_level_1_1, s7_level_1_1}={c8_1, s7_1};
endcase
// Level 2 muxes
always @* // First mux of level2
case(c2_level_1)
1'b0: {c4_level_2, sum[3], sum[2]}={c4_level_1_0,s3_level_1_0, s2_0};
1'b1: {c4_level_2, sum[3], sum[2]}={c4_level_1_1,s3_level_1_1, s2_1};
endcase
always @* // 2nd mux of level2
case(c6_level_1_0)
1'b0: {c8_level_2_0, s7_level_2_0, s6_level_2_0}={c8_level_1_0, s7_level_1_0, s6_0};
1'b1: {c8_level_2_0, s7_level_2_0, s6_level_2_0}={c8_level_1_1, s7_level_1_1, s6_1};
endcase
always @* // 3rd mux of level2
case(c6_level_1_1)
1'b0: {c8_level_2_1, s7_level_2_1, s6_level_2_1}={c8_level_1_0, s7_level_1_0, s6_0};
1'b1: {c8_level_2_1, s7_level_2_1, s6_level_2_1}={c8_level_1_1, s7_level_1_1, s6_1};
endcase
// Level 3 mux
always @*
case(c4_level_2)
1'b0: {cout,sum[7:4]}={c8_level_2_0, s7_level_2_0,s6_level_2_0, s5_level_1_0, s4_0};
1'b1: {cout,sum[7:4]}={c8_level_2_1, s7_level_2_1,s6_level_2_1, s5_level_1_1, s4_1};
endcase
endmodule
// Module for conditional cell
module conditional_cell(a, b, s_0, s_1, c_0, c_1);
input a,b;
output s_0, c_0, s_1, c_1;
assign s_0=a^b; // sum with carry in 0
assign c_0=a&b; // carry with carry in 0
assign s_1=~s_0; // sum with carry in 1
assign c_1=a | b; // carry with carry in 1
endmodule
测试平台：
`timescale 1ns/10ps
module sm8bittry_tb();
parameter w=8;
reg clock,start,reset;
reg [w-1:0] mlier,mcand;
wire [2*w-1:0] prodt;
wire valid;
sm8bittry m2(reset,clock,start,mlier,mcand,prodt,valid);
initial
begin
clock=1;
forever #20 clock = ~clock;
end
initial
begin
start=1;
#40
start=0;
end
initial
begin
$dumpfile("sm8bittry.vcd");
$dumpvars(0,sm8bittry_tb);
#1000 $finish;
end
initial
begin
reset=0;
mlier=8'b10101010;
mcand=8'b11110001;
end
endmodule