Question

我正在尝试编译以下代码，但无论何时我都会收到错误：

'10170 Verilog HDL语法错误在FSM.v（9）附近文本“case”;期待一个操作数'

'10170 Verilog HDL语法错误在FSM.v（9）附近文本“）”;期待“＆lt; =”或“=”'

'10170 Verilog HDL语法错误在FSM.v（11）附近文本“4”;期待“结束”'

module FSM (in0, in1, in2, in3, S, out0, out1, out2, out3); 
input in0, in1, in2, in3, S;
output out0, out1, out2, out3;
reg out0, out1, out2, out3;
always @(in0 or in1 or in2 or in3 or S)
begin
    if(S == 0) begin
    {
        case({in3, in2, in1, in0})
            4'b0000: {out3, out2, out1, out0} = 4'b0000; //0->0
            4'b0001: {out3, out2, out1, out0} = 4'b0011; //1->3
            4'b0010: {out3, out2, out1, out0} = 4'b0110; //2->6
            4'b0011: {out3, out2, out1, out0} = 4'b1001; //3->9
            4'b0100: {out3, out2, out1, out0} = 4'b0010; //4->2
            4'b0101: {out3, out2, out1, out0} = 4'b0101; //5->5
            4'b0110: {out3, out2, out1, out0} = 4'b1000; //6->8
            4'b0111: {out3, out2, out1, out0} = 4'b0001; //7->1
            4'b1000: {out3, out2, out1, out0} = 4'b0100; //8->4
            4'b1001: {out3, out2, out1, out0} = 4'b0111; //9->7
        endcase
    }
    end
    else begin
    {
        case({in3, in2, in1, in0})
            4'b0000: {out3, out2, out1, out0} = 4'b0111; //0->7
            4'b0001: {out3, out2, out1, out0} = 4'b1000; //1->8
            4'b0010: {out3, out2, out1, out0} = 4'b1001; //2->9
            4'b0011: {out3, out2, out1, out0} = 4'b0000; //3->0
            4'b0100: {out3, out2, out1, out0} = 4'b0001; //4->1
            4'b0101: {out3, out2, out1, out0} = 4'b0010; //5->2
            4'b0110: {out3, out2, out1, out0} = 4'b0011; //6->3
            4'b0111: {out3, out2, out1, out0} = 4'b0100; //7->4
            4'b1000: {out3, out2, out1, out0} = 4'b0101; //8->5
            4'b1001: {out3, out2, out1, out0} = 4'b0110; //9->6
        endcase
    }
    end
end
endmodule

对于在case语句中找到的每行代码重复上一个错误。如果有人知道我的错误以及如何解决这个问题我会非常感激！

Answer 1

在{..}条件之后移除大括号（if）。 Verilog不是需要大括号的C，在Verilog中，我们使用begin..end来表示多行程序语句。

此外，建议在自动感知中使用always @(*)（或always_comb（SystemVerilog），而不是always @(in0 or in1 or in2 or in3 or S)的手动感知。

您可能需要详细了解Verilog语法。有关一些信息，请参阅Begin..end链接和always sensitivity question。请参阅IEEE 1364-2001了解Verilog，IEEE 1800-2012了解SystemVerilog。

Answer 2

我认为你不能使用连接操作作为case语句的参数或在赋值的左侧。

所以你需要做这样的事情：

....
reg [3:0] inword, outword;
begin
   inword = {in3, in2, in1, in0};
   if(S == 0) begin
      case (inword)
         4'b0000: outword = 4'b0000; //0->0
         ...
      endcase
   ...
   end
   out3 = outword[3];
   out2 = outword[2];
   out1 = outword[1];
   out0 = outword[0];      
end;

使用If / Else和Case Statements在Verilog中出现错误号10170

2 个答案: