下面给出的是由MATLAB生成的verilog代码，用于找出8x8矩阵的Walsh Hadamrd变换。
module fwhtcustomV2_FixPt
(
clk,
reset,
clk_enable,
y_0,
y_1,
y_2,
y_3,
y_4,
y_5,
y_6,
y_7,
y_8,
y_9,
y_10,
y_11,
y_12,
y_13,
y_14,
y_15,
y_16,
y_17,
y_18,
y_19,
y_20,
y_21,
y_22,
y_23,
y_24,
y_25,
y_26,
y_27,
y_28,
y_29,
y_30,
y_31,
y_32,
y_33,
y_34,
y_35,
y_36,
y_37,
y_38,
y_39,
y_40,
y_41,
y_42,
y_43,
y_44,
y_45,
y_46,
y_47,
y_48,
y_49,
y_50,
y_51,
y_52,
y_53,
y_54,
y_55,
y_56,
y_57,
y_58,
y_59,
y_60,
y_61,
y_62,
y_63,
ce_out,
fwht1_0,
fwht1_1,
fwht1_2,
fwht1_3,
fwht1_4,
fwht1_5,
fwht1_6,
fwht1_7,
fwht1_8,
fwht1_9,
fwht1_10,
fwht1_11,
fwht1_12,
fwht1_13,
fwht1_14,
fwht1_15,
fwht1_16,
fwht1_17,
fwht1_18,
fwht1_19,
fwht1_20,
fwht1_21,
fwht1_22,
fwht1_23,
fwht1_24,
fwht1_25,
fwht1_26,
fwht1_27,
fwht1_28,
fwht1_29,
fwht1_30,
fwht1_31,
fwht1_32,
fwht1_33,
fwht1_34,
fwht1_35,
fwht1_36,
fwht1_37,
fwht1_38,
fwht1_39,
fwht1_40,
fwht1_41,
fwht1_42,
fwht1_43,
fwht1_44,
fwht1_45,
fwht1_46,
fwht1_47,
fwht1_48,
fwht1_49,
fwht1_50,
fwht1_51,
fwht1_52,
fwht1_53,
fwht1_54,
fwht1_55,
fwht1_56,
fwht1_57,
fwht1_58,
fwht1_59,
fwht1_60,
fwht1_61,
fwht1_62,
fwht1_63
);
input clk;
input reset;
input clk_enable;
input [8:0] y_0; // ufix9
input [8:0] y_1; // ufix9
input [8:0] y_2; // ufix9
input [8:0] y_3; // ufix9
input [8:0] y_4; // ufix9
input [8:0] y_5; // ufix9
input [8:0] y_6; // ufix9
input [8:0] y_7; // ufix9
input [8:0] y_8; // ufix9
input [8:0] y_9; // ufix9
input [8:0] y_10; // ufix9
input [8:0] y_11; // ufix9
input [8:0] y_12; // ufix9
input [8:0] y_13; // ufix9
input [8:0] y_14; // ufix9
input [8:0] y_15; // ufix9
input [8:0] y_16; // ufix9
input [8:0] y_17; // ufix9
input [8:0] y_18; // ufix9
input [8:0] y_19; // ufix9
input [8:0] y_20; // ufix9
input [8:0] y_21; // ufix9
input [8:0] y_22; // ufix9
input [8:0] y_23; // ufix9
input [8:0] y_24; // ufix9
input [8:0] y_25; // ufix9
input [8:0] y_26; // ufix9
input [8:0] y_27; // ufix9
input [8:0] y_28; // ufix9
input [8:0] y_29; // ufix9
input [8:0] y_30; // ufix9
input [8:0] y_31; // ufix9
input [8:0] y_32; // ufix9
input [8:0] y_33; // ufix9
input [8:0] y_34; // ufix9
input [8:0] y_35; // ufix9
input [8:0] y_36; // ufix9
input [8:0] y_37; // ufix9
input [8:0] y_38; // ufix9
input [8:0] y_39; // ufix9
input [8:0] y_40; // ufix9
input [8:0] y_41; // ufix9
input [8:0] y_42; // ufix9
input [8:0] y_43; // ufix9
input [8:0] y_44; // ufix9
input [8:0] y_45; // ufix9
input [8:0] y_46; // ufix9
input [8:0] y_47; // ufix9
input [8:0] y_48; // ufix9
input [8:0] y_49; // ufix9
input [8:0] y_50; // ufix9
input [8:0] y_51; // ufix9
input [8:0] y_52; // ufix9
input [8:0] y_53; // ufix9
input [8:0] y_54; // ufix9
input [8:0] y_55; // ufix9
input [8:0] y_56; // ufix9
input [8:0] y_57; // ufix9
input [8:0] y_58; // ufix9
input [8:0] y_59; // ufix9
input [8:0] y_60; // ufix9
input [8:0] y_61; // ufix9
input [8:0] y_62; // ufix9
input [8:0] y_63; // ufix9
output ce_out;
output signed [13:0] fwht1_0; // sfix14_En5
output signed [13:0] fwht1_1; // sfix14_En5
output signed [13:0] fwht1_2; // sfix14_En5
output signed [13:0] fwht1_3; // sfix14_En5
output signed [13:0] fwht1_4; // sfix14_En5
output signed [13:0] fwht1_5; // sfix14_En5
output signed [13:0] fwht1_6; // sfix14_En5
output signed [13:0] fwht1_7; // sfix14_En5
output signed [13:0] fwht1_8; // sfix14_En5
output signed [13:0] fwht1_9; // sfix14_En5
output signed [13:0] fwht1_10; // sfix14_En5
output signed [13:0] fwht1_11; // sfix14_En5
output signed [13:0] fwht1_12; // sfix14_En5
output signed [13:0] fwht1_13; // sfix14_En5
output signed [13:0] fwht1_14; // sfix14_En5
output signed [13:0] fwht1_15; // sfix14_En5
output signed [13:0] fwht1_16; // sfix14_En5
output signed [13:0] fwht1_17; // sfix14_En5
output signed [13:0] fwht1_18; // sfix14_En5
output signed [13:0] fwht1_19; // sfix14_En5
output signed [13:0] fwht1_20; // sfix14_En5
output signed [13:0] fwht1_21; // sfix14_En5
output signed [13:0] fwht1_22; // sfix14_En5
output signed [13:0] fwht1_23; // sfix14_En5
output signed [13:0] fwht1_24; // sfix14_En5
output signed [13:0] fwht1_25; // sfix14_En5
output signed [13:0] fwht1_26; // sfix14_En5
output signed [13:0] fwht1_27; // sfix14_En5
output signed [13:0] fwht1_28; // sfix14_En5
output signed [13:0] fwht1_29; // sfix14_En5
output signed [13:0] fwht1_30; // sfix14_En5
output signed [13:0] fwht1_31; // sfix14_En5
output signed [13:0] fwht1_32; // sfix14_En5
output signed [13:0] fwht1_33; // sfix14_En5
output signed [13:0] fwht1_34; // sfix14_En5
output signed [13:0] fwht1_35; // sfix14_En5
output signed [13:0] fwht1_36; // sfix14_En5
output signed [13:0] fwht1_37; // sfix14_En5
output signed [13:0] fwht1_38; // sfix14_En5
output signed [13:0] fwht1_39; // sfix14_En5
output signed [13:0] fwht1_40; // sfix14_En5
output signed [13:0] fwht1_41; // sfix14_En5
output signed [13:0] fwht1_42; // sfix14_En5
output signed [13:0] fwht1_43; // sfix14_En5
output signed [13:0] fwht1_44; // sfix14_En5
output signed [13:0] fwht1_45; // sfix14_En5
output signed [13:0] fwht1_46; // sfix14_En5
output signed [13:0] fwht1_47; // sfix14_En5
output signed [13:0] fwht1_48; // sfix14_En5
output signed [13:0] fwht1_49; // sfix14_En5
output signed [13:0] fwht1_50; // sfix14_En5
output signed [13:0] fwht1_51; // sfix14_En5
output signed [13:0] fwht1_52; // sfix14_En5
output signed [13:0] fwht1_53; // sfix14_En5
output signed [13:0] fwht1_54; // sfix14_En5
output signed [13:0] fwht1_55; // sfix14_En5
output signed [13:0] fwht1_56; // sfix14_En5
output signed [13:0] fwht1_57; // sfix14_En5
output signed [13:0] fwht1_58; // sfix14_En5
output signed [13:0] fwht1_59; // sfix14_En5
output signed [13:0] fwht1_60; // sfix14_En5
output signed [13:0] fwht1_61; // sfix14_En5
output signed [13:0] fwht1_62; // sfix14_En5
output signed [13:0] fwht1_63; // sfix14_En5
wire enb;
wire [8:0] y [0:63]; // ufix9 [64]
reg signed [13:0] fwht1 [0:63]; // sfix14_En5 [64]
reg signed [13:0] fwhtcustomV2_FixPt_fwht1_1 [0:63]; // sfix14_En5 [64]
reg signed [31:0] fwhtcustomV2_FixPt_slice_temp_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_slice_temp_0_1; // int32
reg signed [14:0] fwhtcustomV2_FixPt_a_1 [0:7]; // sfix15_En3 [8]
reg signed [14:0] fwhtcustomV2_FixPt_c_1 [0:7]; // sfix15_En3 [8]
reg signed [11:0] fwhtcustomV2_FixPt_H_1 [0:7]; // sfix12 [8]
reg signed [10:0] fwhtcustomV2_FixPt_D_1 [0:7]; // sfix11 [8]
reg signed [10:0] fwhtcustomV2_FixPt_C_2 [0:7]; // sfix11 [8]
reg signed [31:0] fwhtcustomV2_FixPt_i_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_0_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_1_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_2_1; // int32
reg [8:0] fwhtcustomV2_FixPt_t_3_1 [0:7]; // ufix9 [8]
reg signed [31:0] fwhtcustomV2_FixPt_t_4_1; // int32
reg [8:0] fwhtcustomV2_FixPt_t_5_1 [0:7]; // ufix9 [8]
reg signed [31:0] fwhtcustomV2_FixPt_t_6_1; // int32
reg [8:0] fwhtcustomV2_FixPt_t_7_1 [0:7]; // ufix9 [8]
reg signed [31:0] fwhtcustomV2_FixPt_t_8_1; // int32
reg [8:0] fwhtcustomV2_FixPt_t_9_1 [0:7]; // ufix9 [8]
reg signed [31:0] fwhtcustomV2_FixPt_t_10_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_11_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_12_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_13_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_14_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_15_1; // int32
reg signed [31:0] fwhtcustomV2_FixPt_t_16_1; // int32
reg signed [63:0] fwhtcustomV2_FixPt_cast_1 [0:7]; // sfix64 [8]
reg signed [63:0] fwhtcustomV2_FixPt_cast_0_1 [0:7]; // sfix64 [8]
reg [9:0] fwhtcustomV2_FixPt_add_temp_1 [0:3]; // ufix10 [4]
reg [9:0] fwhtcustomV2_FixPt_sub_temp_1 [0:3]; // ufix10 [4]
assign y[0] = y_0;
assign y[1] = y_1;
assign y[2] = y_2;
assign y[3] = y_3;
assign y[4] = y_4;
assign y[5] = y_5;
assign y[6] = y_6;
assign y[7] = y_7;
assign y[8] = y_8;
assign y[9] = y_9;
assign y[10] = y_10;
assign y[11] = y_11;
assign y[12] = y_12;
assign y[13] = y_13;
assign y[14] = y_14;
assign y[15] = y_15;
assign y[16] = y_16;
assign y[17] = y_17;
assign y[18] = y_18;
assign y[19] = y_19;
assign y[20] = y_20;
assign y[21] = y_21;
assign y[22] = y_22;
assign y[23] = y_23;
assign y[24] = y_24;
assign y[25] = y_25;
assign y[26] = y_26;
assign y[27] = y_27;
assign y[28] = y_28;
assign y[29] = y_29;
assign y[30] = y_30;
assign y[31] = y_31;
assign y[32] = y_32;
assign y[33] = y_33;
assign y[34] = y_34;
assign y[35] = y_35;
assign y[36] = y_36;
assign y[37] = y_37;
assign y[38] = y_38;
assign y[39] = y_39;
assign y[40] = y_40;
assign y[41] = y_41;
assign y[42] = y_42;
assign y[43] = y_43;
assign y[44] = y_44;
assign y[45] = y_45;
assign y[46] = y_46;
assign y[47] = y_47;
assign y[48] = y_48;
assign y[49] = y_49;
assign y[50] = y_50;
assign y[51] = y_51;
assign y[52] = y_52;
assign y[53] = y_53;
assign y[54] = y_54;
assign y[55] = y_55;
assign y[56] = y_56;
assign y[57] = y_57;
assign y[58] = y_58;
assign y[59] = y_59;
assign y[60] = y_60;
assign y[61] = y_61;
assign y[62] = y_62;
assign y[63] = y_63;
assign enb = clk_enable;
always @* begin
//spssa
//3rd stage
//2nd stage
//1st stage
// x=y(:,i);
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
// %
// Generated by MATLAB 8.1, MATLAB Coder 2.4 and HDL Coder 3.2 %
// %
//%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
for(fwhtcustomV2_FixPt_t_0_1 = 0; fwhtcustomV2_FixPt_t_0_1 <= 7; fwhtcustomV2_FixPt_t_0_1 = fwhtcustomV2_FixPt_t_0_1 + 1) begin
fwhtcustomV2_FixPt_D_1[fwhtcustomV2_FixPt_t_0_1] = 11'sb00000000001;
fwhtcustomV2_FixPt_C_2[fwhtcustomV2_FixPt_t_0_1] = 11'sb00000000001;
end
for(fwhtcustomV2_FixPt_t_1_1 = 0; fwhtcustomV2_FixPt_t_1_1 <= 63; fwhtcustomV2_FixPt_t_1_1 = fwhtcustomV2_FixPt_t_1_1 + 1) begin
fwhtcustomV2_FixPt_fwht1_1[fwhtcustomV2_FixPt_t_1_1] = 14'sb00000000000000;
end
for(fwhtcustomV2_FixPt_i_1 = 0; fwhtcustomV2_FixPt_i_1 <= 7; fwhtcustomV2_FixPt_i_1 = fwhtcustomV2_FixPt_i_1 + 1) begin
fwhtcustomV2_FixPt_cast_1[fwhtcustomV2_FixPt_i_1] = {{29{fwhtcustomV2_FixPt_i_1[31]}}, {fwhtcustomV2_FixPt_i_1, 3'b000}};
fwhtcustomV2_FixPt_slice_temp_1 = fwhtcustomV2_FixPt_cast_1[fwhtcustomV2_FixPt_i_1][31:0];
fwhtcustomV2_FixPt_cast_0_1[fwhtcustomV2_FixPt_i_1] = {{29{fwhtcustomV2_FixPt_i_1[31]}}, {fwhtcustomV2_FixPt_i_1, 3'b000}};
fwhtcustomV2_FixPt_slice_temp_0_1 = fwhtcustomV2_FixPt_cast_0_1[fwhtcustomV2_FixPt_i_1][31:0];
for(fwhtcustomV2_FixPt_t_4_1 = 0; fwhtcustomV2_FixPt_t_4_1 <= 7; fwhtcustomV2_FixPt_t_4_1 = fwhtcustomV2_FixPt_t_4_1 + 1) begin
fwhtcustomV2_FixPt_t_3_1[fwhtcustomV2_FixPt_t_4_1] = y[fwhtcustomV2_FixPt_t_4_1 + fwhtcustomV2_FixPt_slice_temp_1];
fwhtcustomV2_FixPt_t_5_1[fwhtcustomV2_FixPt_t_4_1] = y[fwhtcustomV2_FixPt_t_4_1 + fwhtcustomV2_FixPt_slice_temp_1];
end
for(fwhtcustomV2_FixPt_t_6_1 = 0; fwhtcustomV2_FixPt_t_6_1 <= 3; fwhtcustomV2_FixPt_t_6_1 = fwhtcustomV2_FixPt_t_6_1 + 1) begin
fwhtcustomV2_FixPt_add_temp_1[fwhtcustomV2_FixPt_t_6_1] = fwhtcustomV2_FixPt_t_3_1[fwhtcustomV2_FixPt_t_6_1] + fwhtcustomV2_FixPt_t_5_1[4 + fwhtcustomV2_FixPt_t_6_1];
fwhtcustomV2_FixPt_C_2[fwhtcustomV2_FixPt_t_6_1] = fwhtcustomV2_FixPt_add_temp_1[fwhtcustomV2_FixPt_t_6_1];
end
for(fwhtcustomV2_FixPt_t_8_1 = 0; fwhtcustomV2_FixPt_t_8_1 <= 7; fwhtcustomV2_FixPt_t_8_1 = fwhtcustomV2_FixPt_t_8_1 + 1) begin
fwhtcustomV2_FixPt_t_7_1[fwhtcustomV2_FixPt_t_8_1] = y[fwhtcustomV2_FixPt_t_8_1 + fwhtcustomV2_FixPt_slice_temp_1];
fwhtcustomV2_FixPt_t_9_1[fwhtcustomV2_FixPt_t_8_1] = y[fwhtcustomV2_FixPt_t_8_1 + fwhtcustomV2_FixPt_slice_temp_1];
end
for(fwhtcustomV2_FixPt_t_10_1 = 0; fwhtcustomV2_FixPt_t_10_1 <= 3; fwhtcustomV2_FixPt_t_10_1 = fwhtcustomV2_FixPt_t_10_1 + 1) begin
fwhtcustomV2_FixPt_sub_temp_1[fwhtcustomV2_FixPt_t_10_1] = fwhtcustomV2_FixPt_t_7_1[fwhtcustomV2_FixPt_t_10_1] - fwhtcustomV2_FixPt_t_9_1[4 + fwhtcustomV2_FixPt_t_10_1];
fwhtcustomV2_FixPt_C_2[4 + fwhtcustomV2_FixPt_t_10_1] = fwhtcustomV2_FixPt_sub_temp_1[fwhtcustomV2_FixPt_t_10_1];
end
for(fwhtcustomV2_FixPt_t_11_1 = 0; fwhtcustomV2_FixPt_t_11_1 <= 1; fwhtcustomV2_FixPt_t_11_1 = fwhtcustomV2_FixPt_t_11_1 + 1) begin
fwhtcustomV2_FixPt_D_1[fwhtcustomV2_FixPt_t_11_1] = fwhtcustomV2_FixPt_C_2[fwhtcustomV2_FixPt_t_11_1] + fwhtcustomV2_FixPt_C_2[2 + fwhtcustomV2_FixPt_t_11_1];
end
for(fwhtcustomV2_FixPt_t_12_1 = 0; fwhtcustomV2_FixPt_t_12_1 <= 1; fwhtcustomV2_FixPt_t_12_1 = fwhtcustomV2_FixPt_t_12_1 + 1) begin
fwhtcustomV2_FixPt_D_1[2 + fwhtcustomV2_FixPt_t_12_1] = fwhtcustomV2_FixPt_C_2[fwhtcustomV2_FixPt_t_12_1] - fwhtcustomV2_FixPt_C_2[2 + fwhtcustomV2_FixPt_t_12_1];
end
for(fwhtcustomV2_FixPt_t_13_1 = 0; fwhtcustomV2_FixPt_t_13_1 <= 1; fwhtcustomV2_FixPt_t_13_1 = fwhtcustomV2_FixPt_t_13_1 + 1) begin
fwhtcustomV2_FixPt_D_1[4 + fwhtcustomV2_FixPt_t_13_1] = fwhtcustomV2_FixPt_C_2[4 + fwhtcustomV2_FixPt_t_13_1] + fwhtcustomV2_FixPt_C_2[6 + fwhtcustomV2_FixPt_t_13_1];
end
for(fwhtcustomV2_FixPt_t_14_1 = 0; fwhtcustomV2_FixPt_t_14_1 <= 1; fwhtcustomV2_FixPt_t_14_1 = fwhtcustomV2_FixPt_t_14_1 + 1) begin
fwhtcustomV2_FixPt_D_1[6 + fwhtcustomV2_FixPt_t_14_1] = fwhtcustomV2_FixPt_C_2[4 + fwhtcustomV2_FixPt_t_14_1] - fwhtcustomV2_FixPt_C_2[6 + fwhtcustomV2_FixPt_t_14_1];
end
fwhtcustomV2_FixPt_H_1[0] = fwhtcustomV2_FixPt_D_1[0] + fwhtcustomV2_FixPt_D_1[1];
fwhtcustomV2_FixPt_H_1[1] = fwhtcustomV2_FixPt_D_1[4] + fwhtcustomV2_FixPt_D_1[5];
fwhtcustomV2_FixPt_H_1[2] = fwhtcustomV2_FixPt_D_1[6] + fwhtcustomV2_FixPt_D_1[7];
fwhtcustomV2_FixPt_H_1[3] = fwhtcustomV2_FixPt_D_1[2] + fwhtcustomV2_FixPt_D_1[3];
fwhtcustomV2_FixPt_H_1[4] = fwhtcustomV2_FixPt_D_1[2] - fwhtcustomV2_FixPt_D_1[3];
fwhtcustomV2_FixPt_H_1[5] = fwhtcustomV2_FixPt_D_1[6] - fwhtcustomV2_FixPt_D_1[7];
fwhtcustomV2_FixPt_H_1[6] = fwhtcustomV2_FixPt_D_1[4] - fwhtcustomV2_FixPt_D_1[5];
fwhtcustomV2_FixPt_H_1[7] = fwhtcustomV2_FixPt_D_1[0] - fwhtcustomV2_FixPt_D_1[1];
for(fwhtcustomV2_FixPt_t_15_1 = 0; fwhtcustomV2_FixPt_t_15_1 <= 7; fwhtcustomV2_FixPt_t_15_1 = fwhtcustomV2_FixPt_t_15_1 + 1) begin
fwhtcustomV2_FixPt_a_1[fwhtcustomV2_FixPt_t_15_1] = {fwhtcustomV2_FixPt_H_1[fwhtcustomV2_FixPt_t_15_1], 3'b000};
fwhtcustomV2_FixPt_c_1[fwhtcustomV2_FixPt_t_15_1] = fwhtcustomV2_FixPt_a_1[fwhtcustomV2_FixPt_t_15_1] >> 3;
end
for(fwhtcustomV2_FixPt_t_16_1 = 0; fwhtcustomV2_FixPt_t_16_1 <= 7; fwhtcustomV2_FixPt_t_16_1 = fwhtcustomV2_FixPt_t_16_1 + 1) begin
fwhtcustomV2_FixPt_fwht1_1[fwhtcustomV2_FixPt_t_16_1 + fwhtcustomV2_FixPt_slice_temp_0_1] = {fwhtcustomV2_FixPt_c_1[fwhtcustomV2_FixPt_t_16_1][11:0], 2'b00};
end
end
for(fwhtcustomV2_FixPt_t_2_1 = 0; fwhtcustomV2_FixPt_t_2_1 <= 63; fwhtcustomV2_FixPt_t_2_1 = fwhtcustomV2_FixPt_t_2_1 + 1) begin
fwht1[fwhtcustomV2_FixPt_t_2_1] = fwhtcustomV2_FixPt_fwht1_1[fwhtcustomV2_FixPt_t_2_1];
end
end
assign fwht1_0 = fwht1[0];
assign fwht1_1 = fwht1[1];
assign fwht1_2 = fwht1[2];
assign fwht1_3 = fwht1[3];
assign fwht1_4 = fwht1[4];
assign fwht1_5 = fwht1[5];
assign fwht1_6 = fwht1[6];
assign fwht1_7 = fwht1[7];
assign fwht1_8 = fwht1[8];
assign fwht1_9 = fwht1[9];
assign fwht1_10 = fwht1[10];
assign fwht1_11 = fwht1[11];
assign fwht1_12 = fwht1[12];
assign fwht1_13 = fwht1[13];
assign fwht1_14 = fwht1[14];
assign fwht1_15 = fwht1[15];
assign fwht1_16 = fwht1[16];
assign fwht1_17 = fwht1[17];
assign fwht1_18 = fwht1[18];
assign fwht1_19 = fwht1[19];
assign fwht1_20 = fwht1[20];
assign fwht1_21 = fwht1[21];
assign fwht1_22 = fwht1[22];
assign fwht1_23 = fwht1[23];
assign fwht1_24 = fwht1[24];
assign fwht1_25 = fwht1[25];
assign fwht1_26 = fwht1[26];
assign fwht1_27 = fwht1[27];
assign fwht1_28 = fwht1[28];
assign fwht1_29 = fwht1[29];
assign fwht1_30 = fwht1[30];
assign fwht1_31 = fwht1[31];
assign fwht1_32 = fwht1[32];
assign fwht1_33 = fwht1[33];
assign fwht1_34 = fwht1[34];
assign fwht1_35 = fwht1[35];
assign fwht1_36 = fwht1[36];
assign fwht1_37 = fwht1[37];
assign fwht1_38 = fwht1[38];
assign fwht1_39 = fwht1[39];
assign fwht1_40 = fwht1[40];
assign fwht1_41 = fwht1[41];
assign fwht1_42 = fwht1[42];
assign fwht1_43 = fwht1[43];
assign fwht1_44 = fwht1[44];
assign fwht1_45 = fwht1[45];
assign fwht1_46 = fwht1[46];
assign fwht1_47 = fwht1[47];
assign fwht1_48 = fwht1[48];
assign fwht1_49 = fwht1[49];
assign fwht1_50 = fwht1[50];
assign fwht1_51 = fwht1[51];
assign fwht1_52 = fwht1[52];
assign fwht1_53 = fwht1[53];
assign fwht1_54 = fwht1[54];
assign fwht1_55 = fwht1[55];
assign fwht1_56 = fwht1[56];
assign fwht1_57 = fwht1[57];
assign fwht1_58 = fwht1[58];
assign fwht1_59 = fwht1[59];
assign fwht1_60 = fwht1[60];
assign fwht1_61 = fwht1[61];
assign fwht1_62 = fwht1[62];
assign fwht1_63 = fwht1[63];
assign ce_out = clk_enable;
endmodule // fwhtcustomV2_FixPt
但上面的代码没有优化。我不能在硬件模拟器altera quartus中使用上面的代码，因为它说它使用了超过500个与列出的处理器不兼容的缓冲区。由于我是verilog的新手，我不知道流水线和优化。任何人都可以为我优化这段代码。