Question

我正在尝试为使用重复添加的乘法器编写VHDL代码。这是我写的代码：

library ieee; 
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity FinalProjectDLL is
port (
CLOCK_50, reset : IN std_logic;
A, B : IN std_logic_vector (3 downto 0);
pl, ph, A_disp, B_disp: OUT std_logic_vector (6 downto 0));
end FinalProjectDLL;

architecture behavior of FinalProjectDLL is
type state_type is (s1, s2, s3);
signal state : state_type;

constant delay : integer := 100000000000000000;
constant halfdelay : integer :=delay/2;         
signal count_clock : integer range 0 to delay;
signal clock : std_logic;
signal count : integer;
signal in_project_product: integer;
signal Ai : integer;
signal Bi : integer;

begin
Ai <= conv_integer(A);
Bi <= conv_integer(B);

multi_crtl : process (clock, reset)
begin
if(reset = '0') then
count <= 0;
state <= s1;
elsif(clock'event and clock = '1') then
case state is

when s1 =>    
in_project_product <= 0;
state <= s2;

when s2 =>
if count <= Ai then
in_project_product <= in_project_product + Bi;
count <= count + 1; --VERY WORRIED
state <= s2;
else
state <= s3;
end if;

when s3 =>
pl <= conv_std_logic_vector (in_project_product, 7);
ph <= conv_std_logic_vector(in_project_product, 7);
A_disp <= conv_std_logic_vector(Ai, 7);
B_disp <= conv_std_logic_vector(Bi, 7);
state <= s1;

end case;
end if;
end process; 

clock_divide: process
begin 
wait until clock_50'event and clock_50 = '1';
if count_clock < delay then 
count_clock <= count_clock + 1;
else 
count_clock <= 0;
end if;
if count_clock <  halfdelay then
clock <= '0';
else
clock <= '1';
end if;
end process;

end

代码编译，所以，我认为我已经修复了所有语法错误。我关注的是：我正在使用的代码有一个用if count >= a then格式编写的if循环......发生了什么...... count <= count +1。 count的值会增加并通过if循环直到count = a，就像在C中一样吗？它会在下一个时钟周期发生变化吗？我问，因为我的教授和助教给出了相互矛盾的答案。

如果有人在代码中看到任何与您有关的内容，请告诉我们！谢谢大家，祝你有个美好的一天！

如果count> = A ...... count＆lt; = count +1

0 个答案: