Question

请大家帮我解决这个问题。在我的vhdl代码中，它说行141.解析错误，意外IDENTIFIER对实现检查语法和模拟行为检查语法的说法是141行：语法错误附近＆＃34; K＆＃34; 。我的代码：

    -- Company: 
    -- Engineer: 
    -- 
    -- Create Date:    20:01:29 03/22/2016 
    -- Design Name: 
    -- Module Name:    Counter - Behavioral 
    -- Project Name: 
    -- Target Devices: 
    -- Tool versions: 
    -- Description: 
    --
    -- Dependencies: 
    --
    -- Revision: 
    -- Revision 0.01 - File Created
    -- Additional Comments: 
    --
    --------------------------------------------------------------
    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;

    -- Uncomment the following library declaration if using
    -- arithmetic functions with Signed or Unsigned values
     --use IEEE.NUMERIC_STD.ALL;

     -- Uncomment the following library declaration if instantiating
    -- any Xilinx primitives in this code.
    --library UNISIM;
    --use UNISIM.VComponents.all;

    entity Counter is
      Port ( IN0 : in  STD_LOGIC;
           IN1 : in  STD_LOGIC;
           IN2 : in  STD_LOGIC;
           IN3 : in  STD_LOGIC;
           UDbar : in  STD_LOGIC;
           CLOCK : in  STD_LOGIC;
           LDbar : in  STD_LOGIC;
           RESET : in  STD_LOGIC;
           Q : out  STD_LOGIC_VECTOR (3 downto 0);
           Qbar : out  STD_LOGIC_VECTOR (3 downto 0);
           EN : in  STD_LOGIC);
    end Counter;

    architecture Behavioral of Counter is


    Component DFF is
     Port ( D : in  STD_LOGIC;
        RST : in  STD_LOGIC;
        CLK : in  STD_LOGIC;
        Q : out  STD_LOGIC;
        Qbar : out  STD_LOGIC);
    end component;
    Component MUX4x2 is
     Port ( A : in  STD_LOGIC;
           B : in  STD_LOGIC;
           C : in  STD_LOGIC;
           D : in  STD_LOGIC;
           Sel0 : in  STD_LOGIC;
              Sel1 : in  STD_LOGIC;
              X : out  STD_LOGIC);
     end component;
     signal K,L,M,XS,Qmux,NQmux:std_logic_VECTOR(3 DOWNTO 0);



    begin

    MUX0: MUX4x2 port map
    (A=>Qmux(0),
     B=>NQmux(0),
     C=>IN0,
     D=>IN0,
     Sel0=>M(0),
     Sel1=> NOT (LDbar),
     X=>XS(0));


     MUX1: MUX4x2 port map
     (A=>Qmux(1),
      B=>NQmux(1),
      C=>IN1,
      D=>IN1,
      Sel0=>M(1),
      Sel1=>not (LDbar),
      X=>XS(1));


    MUX2: MUX4x2 port map
    (A=>Qmux(2),
     B=>NQmux(2),
     C=>IN2,
     D=>IN2,
     Sel0=>M(2),
     Sel1=>not LDbar,
     X=>XS(2));


    MUX3: MUX4x2 port map
     (A=>Qmux(3),
      B=>NQmux(3),
      C=>IN3,
      D=>IN3,
      Sel0=>M(3),
      Sel1=>not LDbar,
      X=>XS(3));

    D0: DFF port map
    (D=>XS(0),
     RST=>RESET,
     CLK=>CLOCK,
     Q=>Qmux(0),
     Qbar=>NQmux(0));

     D1: DFF port map
    (D=>XS(1),
     RST=>RESET,
     CLK=>CLOCK,
     Q=>Qmux(1),
     Qbar=>NQmux(1));

     D2: DFF port map
     (D=>XS(2),
      RST=>RESET,
      CLK=>CLOCK,
      Q=>Qmux(2),
      Qbar=>NQmux(2));

      D3: DFF port map
     (D=>XS(3),
      RST=>RESET,
      CLK=>CLOCK,
      Q=>Qmux(3),
      Qbar=>NQmux(3));



      process( K,L,Qmux,RESET,CLOCK,LDbar,UDbar,EN )


      K(0)<=UDbar AND EN;----------------!!!!this line!!!!!---------------------
      L(0)<=(NOT UDbar) AND EN;
      M(0)<=K(0)OR L(0);
      K(1)<=EN AND Qmux(0) AND UDbar;
      L(1)<=EN AND Qmux(0) AND (NOT UDbar);
      M(1)<=K(1) OR L(1);
      K(2)<=EN AND Qmux(0) AND Qmux(1) AND UDbar;
      L(2)<=EN AND Qmux(0)AND Qmux(1) AND (NOT UDbar);
      M(2)<=K(2) OR L(2);
      K(3)<=EN AND Qmux(0) AND Qmux(1) AND Qmux(2) AND UDbar;
      L(3)<=EN AND Qmux(0)AND Qmux(1) AND Qmux(2) AND (NOT UDbar);
      M(3)<=  (K(3) OR L(3));
      IN3 = '0';
      IN2= '0';
      IN1= '1';
      IN0= '1';

     Wait until (CLOCK'Event AND CLOCK = '1'); 

     If RESET='1' AND LDbar='1' AND EN='0' Then 
     Qmux(0)= '0' AND Qmux(1)= '0' AND Qmux(2)= '0' AND Qmux(3)= '0';

     Elsif RESET='1' AND LDbar='0' AND EN='0' Then 
     Qmux(0)= '0' AND Qmux(1)= '0' AND Qmux(2)= '0' AND Qmux(3)= '0';

     Elsif RESET='0' AND LDbar='0' AND EN='0' Then   
     Qmux(0)= '0' AND Qmux(1)= '0' AND Qmux(2)= '1' AND Qmux(3)= '1';

     end if;
     end process;


   end behavioral;

Answer 1

您在begin行后缺少process(K,L, ...)语句。

在显示错误的行之前必须查看行。错误消息中的行号并不总是您犯了错误的行。

Answer 2

我教VHDL。错过begin似乎是一个常见的错误。 VHDL中的许多结构具有类似的三线结构

<something>
  -- declare stuff here
begin
  -- do stuff here
end <something>;

例如：

process
  -- declare stuff here (eg constant, variable, procedure declarations)
begin
  -- sequential code here
end process;

和

architecture
  -- declare stuff here (eg constant, variable declarations)
begin
  -- concurrent code here
end architecture;

和

function
  -- declare stuff here (eg constant, variable declarations)
begin
  -- sequential code here
end function;

和

procedure
  -- declare stuff here
begin
  -- sequential code here
end procedure;

Answer 3

马修泰勒和scary_jeff都没有给你一个工作设计，有更多的语法错误

除了begin之外，我对流程进行了一些更改：

    process ( k, l, qmux, nqmux, udbar, en) -- reset, clock, ldbar, udbar, en )
    begin  -- added per scary_jeff, matthew taylor

        -- k(0) <= udbar and en;  ---!!!!this line!!!!!-----
        -- l(0) <= not udbar and en;
        -- m(0) <= k(0) or l(0);
        -- m(0) <= en;               -- inverts qmux(0) for up or down

        k(1) <= en and qmux(0)  and     udbar;
        l(1) <= en and nqmux(0) and not udbar;  -- nqmux not qmux
        m(1) <= k(1) or l(1);

        -- m(1) <= en and  (
        --                  ( qmux(0)  and     udbar) or
        --                  ( nqmux(0) and not udbar)
        --                 );

        k(2) <= en and qmux(0)  and qmux(1)  and     udbar;
        l(2) <= en and nqmux(0) and nqmux(1) and not udbar; -- nqmux not qmux
        m(2) <= k(2) or l(2);

        k(3) <= en and qmux(0)  and qmux(1)  and qmux(2)  and     udbar;
        l(3) <= en and nqmux(0) and nqmux(1) and nqmux(2) and not udbar; -- nqmux
        m(3) <=  k(3) or l(3);

        -- in3 = '0';  -- These are input ports and signals ( use "<=" )
        -- in2 = '0';
        -- in1 = '1';
        -- in0 = '1';

    -- wait until clock'event and clock = '1';  -- none of this is used

        -- if reset = '1' and ldbar = '1' and en = '0' then 
        -- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';

        -- elsif reset='1' and ldbar='0' and en='0' then
        -- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '0' and qmux(3)= '0';
        --
        -- elsif reset='0' and ldbar='0' and en = '0' then
        -- qmux(0)= '0' and qmux(1)= '0' and qmux(2)= '1' and qmux(3)= '1';
        --
        -- end if;
    end process;


    q <= qmux;       -- added
    qbar <= nqmux;   -- added

end architecture behavioral;

值得注意的是，您在右侧的计数器位上为所有'1'设置了递增和递减值。我认为udbar的意思是'1'代表向上，'0'代表向下。

你可以看到我缩小了敏感度列表，注释掉if语句和wait语句是不需要的，也没有使用。

您也无法分配到输入端口，并且不应在qmux上有多个驱动程序。

有几点要点。

m（0）的两个术语是相同的，您可以将其简化为enable（en）。

你不需要中间词l和k，我把它们留进去。注意我减少了l，m和k的长度并直接连接到MUX0：

signal k, l, m:         std_Logic_vector (3 downto 1);
signal xs, qmux, nqmux: std_logic_vector (3 downto 0);

mux0:                      -- swap inputs to use ldbar directly
    mux4x2 
        port map ( 
            a => in0,      -- was qmux(0),
            b => in0,      -- was nqmux(0),
            c => qmux(0),  -- was in0,
            d => nqmux(0), -- was in0,
            sel0 => en,    -- was m(0),     -- an optimization
            sel1 => ldbar, -- was not ldbar
            x => xs(0)
        );
mux1: 
    mux4x2 
        port map (
            a => in1,      -- was qmux(1),
            b => in1,      -- was nqmux(1),
            c => qmux(1),  -- was in1,
            d => nqmux(1), -- was in1,
            sel0 => m(1),
            sel1 => ldbar, -- was not ldbar
            x => xs(1)
        );
mux2: 
    mux4x2 
        port map (
            a => in2,      -- was qmux(2),
            b => in2,      -- was nqmux(2),
            c => qmux(2),  -- was in2,
            d => nqmux(2), -- was in2,
            sel0 => m(2),
            sel1 => ldbar, -- was not ldbar
            x => xs(2)
        );
mux3: 
    mux4x2 
        port map (
            a => in3,      -- was qmux(3),
            b => in3,      -- was nqmux(3),
            c => qmux(3),  -- was in3,
            d => nqmux(3), -- was in3,
            sel0 => m(3),
            sel1 => ldbar, -- was not ldbar
            x => xs(3)
        );

我还将a，b和c，d输入交换到多路复用器，以使用ldbar作为sel1。要求实际是静态表达式。

这些变化以及一个genned up testbench，mux4x2和dff假定为正复位给出：

一个工作的上升计数器。

所以那里的设计是99％。除了进程开始之外的错误没有得到在qmux（n）和nqmux（n）之间切换的增量和减量值，以及过程中的一些死木。

哦，请注意两个添加的并发信号分配，将qmux分配给q，nqmux分配给计数器中进程以下的qbar。

我会做一些不同的事情，没有中间信号表示m（3 downto 1），in0 - in 1可能是inp（3 downto 0）。

测试平台：

library ieee;
use ieee.std_logic_1164.all;

entity counter_ud_tb is
end entity;

architecture foo of counter_ud_tb is
    signal in0:    std_logic := '1';  -- load value "1111"
    signal in1:    std_logic := '1';
    signal in2:    std_logic := '1';
    signal in3:    std_logic := '1';
    signal udbar:  std_logic;
    signal clock:  std_logic := '0';
    signal ldbar:  std_logic;
    signal reset:  std_logic;
    signal q:      std_logic_vector (3 downto 0);
    signal qbar:   std_logic_vector (3 downto 0);
    signal en:     std_logic;

begin
DUT:
    entity work.counter
        port map (
            in0 => in0,
            in1 => in1,
            in2 => in2,
            in3 => in3,
            udbar => udbar,
            clock => clock,
            ldbar => ldbar,
            reset => reset,
            q => q,
            qbar => qbar,
            en => en
        );
CLKGEN:
    process
    begin
        wait for 5 ns;
        clock <= not clock;
        if now > 380 ns then
            wait;
        end if;
    end process;

STIMULI:
    process
    begin
        wait for 6 ns;
        reset <= '1';
        ldbar <= '1';
        en <= '0';
        udbar <= '1';  -- up
        wait for 20 ns;
        reset <= '0';
        ldbar <= '0';
        wait for 10 ns;
        ldbar <= '1';
        wait for 10 ns;
        en <= '1';  
        wait for 160 ns;
        udbar <= '0';  -- down
        wait for 160 ns;
        en <= '0';
        wait;
    end process;
end architecture;

第141行。解析错误，意外IDENTIFIER

3 个答案: