java.utilNoSuchElementException:Vec的None.get

时间:2016-03-03 22:14:08

标签: chisel

也许我正在以错误的方式做事。作为状态机行为的一部分,我有许多需要锁定和解锁的缓冲区。我认为使用Vec of Reg来存储状态从一个时钟到一个时钟并使用var Vec的线来累积状态,因为状态机会锁定和解锁东西。这里的代码类似于我写的代码,它以相同的方式中断:

import Chisel._

class testvec extends Module
{
    val io = new Bundle
    {
        val addr    = Vec( 5, UInt( INPUT, 4 ) )
        val enable  = Bool( INPUT )
        val in      = Vec( 5, UInt( INPUT, 16 ) )
        val out     = Vec( 16, UInt( OUTPUT, 16 ) )
    }

    val latch = Vec( 16, Reg( init=UInt(0,16) ) )
    var temp = Vec( 16, UInt(0,16) )
    for( i <- 0 until 16 )
    {
        temp(i) := latch(i)
    }
    for( i <- 0 until 5 )
    {
        temp(io.addr(i)) := io.in(i)
    }
    for( i <- 0 until 16 )
    {
        io.out(i) := temp(i)
    }
    when( io.enable )
    {
        for( i <- 0 until 16 )
        {
            latch(i) := temp(i)
        }
    }
}

class testvec_Tests(c: testvec) extends Tester(c)
{
    step( 1 )
}

object mainStub
{
    def main( args: Array[String] ): Unit =
    {
        chiselMainTest( Array[String]("--backend", "c", // "--backend", "v",
                "--compile", "--test", "--genHarness"),
                () => Module( new testvec() ) )
        {
            c => new testvec_Tests( c )
        }
    }
}

请注意,虽然这段代码只有一个简单的循环,但我需要在每个时钟周期执行状态机的过程中在各个点获得组合锁定状态,这就是为什么这种简化将这些组合状态作为最终输出而不是寄存器。

以下是错误消息的全文:

[info] Set current project to chisel
[info] Running mainStub 
[error] (run-main-0) java.util.NoSuchElementException: None.get
java.util.NoSuchElementException: None.get
    at scala.None$.get(Option.scala:347)
    at scala.None$.get(Option.scala:345)
    at Chisel.ROMData$$anonfun$3.apply(ROM.scala:90)
    at Chisel.ROMData$$anonfun$3.apply(ROM.scala:90)
    at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
    at scala.collection.Iterator$class.foreach(Iterator.scala:750)
    at scala.collection.immutable.RedBlackTree$TreeIterator.foreach(RedBlackTree.scala:468)
    at scala.collection.MapLike$DefaultValuesIterable.foreach(MapLike.scala:206)
    at scala.collection.TraversableLike$class.map(TraversableLike.scala:245)
    at scala.collection.AbstractTraversable.map(Traversable.scala:104)
    at Chisel.ROMData.<init>(ROM.scala:90)
    at Chisel.ROM.data$lzycompute(ROM.scala:72)
    at Chisel.ROM.data(ROM.scala:72)
    at Chisel.ROM.read(ROM.scala:77)
    at Chisel.Vec.apply(Vec.scala:121)
    at testvec$$anonfun$2.apply$mcVI$sp(testvec.scala:21)
    at scala.collection.immutable.Range.foreach$mVc$sp(Range.scala:166)
    at testvec.<init>(testvec.scala:19)
    at mainStub$$anonfun$main$1$$anonfun$apply$1.apply(testvec.scala:47)
    at mainStub$$anonfun$main$1$$anonfun$apply$1.apply(testvec.scala:47)
    at Chisel.Module$.Chisel$Module$$init(Module.scala:65)
    at Chisel.Module$.apply(Module.scala:50)
    at mainStub$$anonfun$main$1.apply(testvec.scala:47)
    at mainStub$$anonfun$main$1.apply(testvec.scala:47)
    at Chisel.Driver$.execute(Driver.scala:101)
    at Chisel.Driver$.apply(Driver.scala:41)
    at Chisel.Driver$.apply(Driver.scala:64)
    at Chisel.chiselMain$.apply(hcl.scala:63)
    at Chisel.chiselMainTest$.apply(hcl.scala:76)
    at mainStub$.main(testvec.scala:48)
    at mainStub.main(testvec.scala)
    at sun.reflect.NativeMethodAccessorImpl.invoke0(Native Method)
    at sun.reflect.NativeMethodAccessorImpl.invoke(NativeMethodAccessorImpl.java:57)
    at sun.reflect.DelegatingMethodAccessorImpl.invoke(DelegatingMethodAccessorImpl.java:43)
    at java.lang.reflect.Method.invoke(Method.java:606)
[trace] Stack trace suppressed: run last compile:run for the full output.
java.lang.RuntimeException: Nonzero exit code: 1
    at scala.sys.package$.error(package.scala:27)
[trace] Stack trace suppressed: run last compile:run for the full output.
[error] (compile:run) Nonzero exit code: 1
[error] Total time: 1 s, completed Mar 3, 2016 1:49:17 PM

1 个答案:

答案 0 :(得分:1)

你确定你的“Vec”声明吗? 根据{{​​3}},我认为Vec必须声明如下:

val io = new Bundle
{
    val addr    = Vec.fill(5) {UInt( INPUT, 4 )}
    val enable  = Bool( INPUT )
    val in      = Vec.fill( 5 ) {UInt( INPUT, 16 )}
    val out     = Vec.fill( 16 ) {UInt( OUTPUT, 16 )}
}