我在vhdl中为audioloopback编写代码并在地图中收到错误,如下所示:
错误:MapLib:979 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有输入信号" Mmux_ac97_sdata_out23"
哪一个 将被修剪。有关原因的详细信息,请参见地图报告文件的第5部分 输入信号将变为未驱动 错误:MapLib:979 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)具有输入信号" Madd_bit_count_lut< 6>"哪一个 将被修剪。有关原因的详细信息,请参见地图报告文件的第5部分 输入信号将变为未驱动 错误:MapLib:979 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)具有输入信号" Madd_bit_count_lut< 7>"哪一个 将被修剪。有关原因的详细信息,请参见地图报告文件的第5部分 输入信号将变为未驱动 错误:MapLib:979 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有输入信号 " BIT_COUNT [7] _GND_4_o_LessThan_9_o"将被修剪。见第5节 有关输入信号变为何处的详细信息,请参见地图报告文件 无驱动。
错误:MapLib:979 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)具有输入信号" ac97_sync_OBUF"这将是 修剪。有关输入原因的详细信息,请参见“地图报告文件”的第5部分 信号将变为未驱动 错误:MapLib:978 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有一个使用输入引脚I0的公式,其中没有 更长的连接信号。请确保使用的所有引脚 该LUT的等式具有未被修整的信号(参见第5节) 有关修剪信号的详细信息,请参见报告文件 错误:MapLib:978 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有一个使用输入引脚I1的公式,其中没有 更长的连接信号。请确保使用的所有引脚 该LUT的等式具有未被修整的信号(参见第5节) 有关修剪信号的详细信息,请参见报告文件 错误:MapLib:978 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有一个使用输入引脚I2的公式,其中没有 更长的连接信号。请确保使用的所有引脚 该LUT的等式具有未被修整的信号(参见第5节) 有关修剪信号的详细信息,请参见报告文件 错误:MapLib:978 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有一个使用输入引脚I3的公式,其中没有 更长的连接信号。请确保使用的所有引脚 该LUT的等式具有未被修整的信号(参见第5节) 有关修剪信号的详细信息,请参见报告文件 错误:MapLib:978 - LUT6符号" Mmux_ac97_sdata_out210" (输出 signal = ac97_sdata_out_OBUF)有一个使用输入引脚I5的公式,其中没有 更长的连接信号。请确保使用的所有引脚 该LUT的等式具有未被修整的信号(参见第5节) 有关修剪信号的详细信息,请参见报告文件。
-- Company:
-- Engineer:
--
-- Create Date: 14:35:54 02/28/2016
-- Design Name:
-- Module Name: audioloopbackVHDL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity audioloopbackVHDL is
port (
clock :in std_logic;
ac97_sdata_out :out std_logic;
ac97_sdata_in :in std_logic;
ac97_sync :out std_logic;
audio_reset_b :out std_logic;
ac97_bit_clock :in std_logic);
end audioloopbackVHDL;
architecture Behavioral of audioloopbackVHDL is
--attribute S: string;
--attribute S of ac97_sdata_out: signal is "TRUE";
signal abc : std_logic_vector (7 downto 0);
signal def : integer;
signal ghi : std_logic_vector (7 downto 0);
signal jkl : integer;
signal command_address : std_logic_vector(19 downto 0);
signal command_data : std_logic_vector(19 downto 0);
signal bit_count : std_logic_vector(7 downto 0) := "00000000";
signal frame_count : std_logic_vector(3 downto 0) := "0000";
signal command : std_logic_vector(23 downto 0);
signal reset_count : std_logic_vector(7 downto 0) := "00000000";
signal count : std_logic_vector(18 downto 0);
signal enable : std_logic_vector(19 downto 0);
signal en1 : std_logic_vector(17 downto 0);
begin
process(clock)
begin
if(rising_edge(clock))then
if(reset_count <= "11111111")then
audio_reset_b <= '1';
else
reset_count <= std_logic_vector(unsigned(reset_count) + 1 );
end if;
end if;
end process;
process(bit_count, ac97_bit_clock, command_data, command_address, frame_count)
begin
-- Generate the sync signal
if (bit_count <= "11111111")then
ac97_sync <= '1';
end if;
if (bit_count <= "00001111")then
ac97_sync <= '0';
end if;
if ((bit_count >= "00000000") and (bit_count <= "00001111"))then
-- Slot 0: Tags
case bit_count is
when "00000000" => ac97_sdata_out <= '1';
when "00000001" => ac97_sdata_out <= '1';
when "00000010" => ac97_sdata_out <= '1';
when others => ac97_sdata_out <= '0';
end case;
elsif ((bit_count >= "00010000") and (bit_count <= "00100011"))then
-- Slot 1: Command address
abc <= std_logic_vector(35 - unsigned(bit_count));
def <= to_integer(unsigned(abc));
ac97_sdata_out <= command_address(def);
elsif ((bit_count >= "00100100") and (bit_count <= "00110111"))then
-- Slot 2: Command data
ghi <= std_logic_vector(55 - unsigned(bit_count));
jkl <= to_integer(unsigned(ghi));
ac97_sdata_out <= command_data(jkl);
else
ac97_sdata_out <= '0';
end if;
if (bit_count <= "11111111")then
frame_count <= std_logic_vector(unsigned(frame_count) + 1);
bit_count <= std_logic_vector(unsigned(bit_count) + 1);
end if;
end process;
process(frame_count, command, ac97_bit_clock, count, command_address, command_data, ac97_sdata_in)
begin
case frame_count is
when "0000" => command <= "000000100000000000000000"; -- Unmute line outputs
when "0001" => command <= "000001000000000000000000"; -- Unmute headphones
when "0010" => command <= "000100000000100000001000"; -- Unmute line inputs
when others => command <= "111111000000000000000000"; -- Read vendor ID
end case;
-- Separate the address and data portions of the command
-- and pad them to 20 bits
command_address(19 downto 12) <= command(23 downto 16);
command_address(11 downto 0) <= "000000000000";
command_data(19 downto 4) <= command(15 downto 0);
command_data(3 downto 0) <= "0000";
end process;
end architecture;
和ucf文件是:
NET "clock" LOC=V10 | IOSTANDARD=LVCMOS33 | CLOCK_DEDICATED_ROUTE=FALSE;
#
# Audio CODEC
#
NET "audio_reset_b" LOC=K15 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "ac97_sdata_out" LOC=H18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "ac97_sdata_in" LOC=J16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "ac97_sync" LOC=K16 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST ;
NET "ac97_bit_clock" LOC=J18 | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST | CLOCK_DEDICATED_ROUTE=FALSE;
答案 0 :(得分:0)
您的设计中有(至少一个)组合循环。你从顶部开始的第三个过程基本上是
process (bit_count, frame_count)
begin
frame_count <= frame_count + 1;
bit_count <= bit_count + 1;
end process;
您是否忘记等待时钟改变?