Question

我正在CoolRunner 2上进行一个60分钟计时器的小项目。我想驱动四个7段显示器以开发我的VHDL新技能，我主要是一个模拟工程师，所以如果你有任何关于我的提示VHDL，我会向他们开放。但我的问题是：我有四个计数器，它们一起计数到59分钟和59秒然后重置但我的第三个计数器没有增加（counter3）。当我运行测试平台时，它只会达到59秒，然后重置。

下面我附上了计数器1,2,3,4的计数器代码。有人可以看到任何拼写错误或明显错误吗？

--counter1-------------------------------------------------------------     
Process ( CLK1Hz,RST,SW1,overflow4 )
begin
    if (RST = '0') or (overflow4 = '1')  then
        Counter1 <=0;
    elsif Rising_edge (CLK1Hz)then
        if (SW1 = '1' )  then
            counter1 <= counter1 + 1;
                if Counter1 = 8 then
                    overflow1 <= '1';
                elsif counter1 = 9 then
                    Counter1 <= 0;
                    overflow1 <= '0';
                end if;
        end if;
end if;
end process;

--counter2---------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
begin
    if (RST = '0') or (overflow4 = '1') then
        Counter2 <=0;
    elsif Rising_edge (CLK1Hz) then
        if (SW1 = '1' ) and (overflow1 = '1') then
            counter2 <= counter2 + 1;
                if counter2 = 5 and counter1 = 8 then
                    overflow2 <= '1';
                elsif counter2 = 5 and counter1 = 9 then
                    counter2 <= 0;
                    overflow2 <= '0';
                end if;
        end if;     
end if;
end process;

--counter3----------------------------------------------------------------   
Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
begin
   if (RST = '0') or (overflow4 = '1') then
    Counter3 <=0;
   elsif Rising_edge (CLK1Hz) then
        if (SW1 = '1' ) and (overflow2 = '1') then
            counter3 <= counter3 + 1;
                if counter3 = 9 and counter2 = 5 and counter1 = 8 then
                    overflow3 <= '1';
                elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
                    counter3 <= 0;
                    overflow3 <= '0';
                end if;
        end if;
end if;
end process;    

--counter4----------------------------------------------------------------
Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
begin
    if (RST = '0') or (overflow4 = '1') then
        Counter4 <=0;
    elsif Rising_edge (CLK1Hz) then
        if(SW1 = '1' ) and (overflow3 = '1') then
            counter4 <= counter4 + 1;
                if counter4 = 6 then
                    counter4 <= 0;
                    overflow4 <= '1';
                else overflow4 <= '0';
                end if;
        end if;
end if;
end process;

更新1：问题似乎是Integer无法接受并且正常运行，所以我试图将其转换为无符号，但这并没有解决问题。

Answer 1

计数器3没有递增，因为overflow2永远不会设置为＆＃39; 1＆＃39;。让我们来看看counter2的过程的时钟同步部分：

    if (SW1 = '1' ) and (overflow1 = '1') then
        counter2 <= counter2 + 1;
            if counter2 = 5 and counter1 = 8 then
                overflow2 <= '1';
            elsif counter2 = 5 and counter1 = 9 then
                counter2 <= 0;
                overflow2 <= '0';
            end if;
    end if;

仅在overflow2，SW = '1'，overflow1 = '1'和counter2 = 5时设置注册counter1 = '8'。但是，overflow1 = '1'和counter1 = 8在同一时间永远不会成立。当overflow1的旧值为8时设置了注册counter1，但overflow1将为＆＃39; 1＆＃39; 仅和counter1 = 9一起。

您必须在此过程中修复if语句的嵌套，这样，只有counter2的增量取决于overflow1。设置overflow2必须仅取决于计数器状态（和SW1）。所以，上面的内容必须改为：

  if (SW1 = '1' ) then
    if (overflow1 = '1') then
      counter2 <= counter2 + 1;
    end if;

    if counter2 = 5 and counter1 = 8 then
      overflow2 <= '1';
    elsif counter2 = 5 and counter1 = 9 then
      counter2 <= 0;
      overflow2 <= '0';
    end if;
  end if;

同样适用于counter3和counter4的流程。

在最后一个过程中，只能设置信号overflow4，因为一旦设置，异步复位将永久执行。如您所述，只需使用counter4的同步重置即可。 overflow4还应重置其他计数器同步，但我会将此作为练习。

总而言之，您将获得以下代码嵌入到具有时钟生成的测试平台中：

library ieee;
use ieee.std_logic_1164.all;

entity counter2 is
end entity counter2;

architecture counter2 of counter2 is
  signal counter1, counter2, counter3, counter4 : integer := 0;
  signal overflow1, overflow2, overflow3, overflow4 : std_logic := '0';
  signal RST : std_logic := '1';
  signal SW1 : std_logic := '1';
  signal CLK1Hz : std_logic := '1';

begin  -- architecture counter2

  -- clock generation
  CLK1Hz <= not CLK1Hz after 500 ms;

--counter1-------------------------------------------------------------     
  Process ( CLK1Hz,RST,SW1,overflow4 )
  begin
    if (RST = '0') or (overflow4 = '1')  then
      Counter1 <=0;
    elsif Rising_edge (CLK1Hz)then
      if (SW1 = '1' )  then
        counter1 <= counter1 + 1;
        if Counter1 = 8 then
          overflow1 <= '1';
        elsif counter1 = 9 then
          Counter1 <= 0;
          overflow1 <= '0';
        end if;
      end if;
    end if;
  end process;

--counter2---------------------------------------------------------------
  Process ( CLK1Hz,RST,SW1,overflow1,overflow4,counter1 )
  begin
    if (RST = '0') or (overflow4 = '1') then
      Counter2 <=0;
    elsif Rising_edge (CLK1Hz) then
      if (SW1 = '1' ) then
        if (overflow1 = '1') then
          counter2 <= counter2 + 1;
        end if;
        if counter2 = 5 and counter1 = 8 then
          overflow2 <= '1';
        elsif counter2 = 5 and counter1 = 9 then
          counter2 <= 0;
          overflow2 <= '0';
        end if;
      end if;     
    end if;
  end process;

--counter3----------------------------------------------------------------   
  Process ( CLK1Hz,RST,SW1,overflow2,overflow4,counter1,counter2 )
  begin
    if (RST = '0') or (overflow4 = '1') then
      Counter3 <=0;
    elsif Rising_edge (CLK1Hz) then
      if (SW1 = '1' ) then
        if (overflow2 = '1') then
          counter3 <= counter3 + 1;
        end if;

        if counter3 = 9 and counter2 = 5 and counter1 = 8 then
          overflow3 <= '1';
        elsif counter3 = 9 and counter2 = 5 and counter1 = 9 then
          counter3 <= 0;
          overflow3 <= '0';
        end if;
      end if;
    end if;
  end process;    

--counter4----------------------------------------------------------------
  Process ( CLK1Hz,RST,SW1,overflow3,overflow4,counter1,counter2,counter3 )
  begin
    if (RST = '0') then-- or (overflow4 = '1') then
      Counter4 <=0;
    elsif Rising_edge (CLK1Hz) then
      if(SW1 = '1' ) then
        if (overflow3 = '1') then
          counter4 <= counter4 + 1;
        end if;

        if counter4 = 6 then
          counter4 <= 0;
          overflow4 <= '1';
        else overflow4 <= '0';
        end if;
      end if;
    end if;
  end process;

end architecture counter2;

以下是前100秒模拟的屏幕截图：

柜台溢出或条件不是肉

1 个答案: