Question

以下是我对简单仲裁者

的代码

        module arbiter(clk,rst,req,grnt,req_val);
    input clk;
    input rst;
    input [3:0] req;
    input [3:0] req_val;
    output [3:0] grnt;

    int j;
    int i;
    parameter A = 2'd0;
    parameter B = 2'd1;
    parameter C = 2'd2;
    parameter D = 2'd3;
    logic [1:0] current_state; 
    logic [1:0] next_state;
    always_comb
    begin
    case (current_state)
        D:
        begin
            grnt = 4'b1000; 
            j = 0;
            for (i = 0; i<4;i++) begin

                if (req[(j+i) % 4 ] == 1) 
                    break;
            end
            case (i)
                0: next_state = A;
                1: next_state = B;
                2: next_state = C;
                3: next_state = D;
            endcase
        end
        A:
        begin
            j = 1;
            grnt = 4'b001; 
            for (i = 0; i<4;i++) begin
                if (req[(i+j) % 4] == 1) 
                    break;
            end
            case (i)
                0: next_state = A;
                1: next_state = B;
                2: next_state = C;
                3: next_state = D;
            endcase
        end
        B:
        begin
            j = 2;
            grnt = 4'b0010; 
            for (i = 0; i<4;i++ ) begin
                if (req[(i+j) % 4] == 1) 
                    break;

            end
            case (i)
                0: next_state = A;
                1: next_state = B;
                2: next_state = C;
                3: next_state = D;
            endcase
        end
        C:
        begin
            j = 3;
            grnt = 4'b0100; 
            for (i = 0; i<4;i++ ) begin
                if (req[(i+j)% 4] == 1) 
                    break;

            end
            case (i)
                0: next_state = A;
                1: next_state = B;
                2: next_state = C;
                3: next_state = D;
            endcase
        end
    endcase
    end
    endmodule


    always_ff@(posedge clk)
    begin
    current_state <= next_state;
    end
endmodule

我收到以下错误：

arbitrer.sv（21）:( vlog-2110）非法引用net＆＃34; grnt＆＃34;。

和

arbitrer.sv（87）：near＆＃34; always_ff＆＃34 ;:语法错误，意外的always_ff，期待上课。

所以grnt错了吗？我不能直接分配给模块输出？

Answer 1

您的代码存在两个问题。

您在代码中使用过两次endmodule语句。只需在第86行注释掉一个。
您还没有为grnt变量定义数据类型，因此默认情况下，wire和wire不能使用reg和logic在always块中，因此将其声明为Counting objects: 40, done. Delta compression using up to 8 threads. Compressing objects: 100% (39/39), done. Writing objects: 100% (40/40), 73.81 MiB | 4.00 KiB/s, done. Total 40 (delta 12), reused 0 (delta 0) / $ git config http.postBuffer 524288000。

＆＃34;非法提及网络＆＃34; systemverilog中的错误 - 试图设计简单的仲裁者

1 个答案: