Question

我已经在这一点上受到了很长一段时间的打击，如果有人可以调查并解决它，我会真的帮助我。系统有4个输入 - w，a，b，c。所有都是周期性输入，随时间变化。输出是o。全部存储为带符号的16位寄存器。当w小于16'b0000101100110011时，输出（o）直接等于'a'。当w大于此值时，输出变为'b'，但这发生在c的过零期间，即当它从正变为负时，反之亦然。因此，即使w大于上述指定值但c未超过其零交叉，输出“o”仍将继续为“a”。我试图看到'c'的MSB值。一旦它改变了它的值，我试图将输出从'a'改为'b'，但这不会按照给定的代码发生：

module trial(clk, w, a, b, c, o
    );

input clk;    
input signed [15:0] w;    
input signed [15:0] a;    
input signed [15:0] b;    
input signed [15:0] c;    
output signed [15:0] o;    
reg signed [15:0] temp;    
reg signed [15:0] temp1;    
reg signed [15:0] temp2;    


always @(posedge clk)    
 begin    
  if (w<16'b0000101100110011)    
   begin    
    temp = a;    
   end    
  else    
   begin    
    temp1 = 0;//Initializing the value of temp1    
    temp2 = 0;//Initializing the value of temp2      
    while (temp1 == temp2)    
     begin    
      temp1 = c[15];// storing the sign bit of input 'c'    
      repeat(1) @(posedge clock);// one clock cycle delay command (##1 was    not working)    
      temp2 = c[15];//storing the sign bit of input 'c' after one clock cycle    
     end    
    temp = b;    
   end    
  end    
 assign o = temp;    
endmodule

当'w'变得大于16'b0000101100110011时，输出立即从'a'变为'b'。它不会等待'c'的过零点。如果有一些错误并且可能是一个解决方案，有人可以指出。感谢

Answer 1

我认为这样的事情也会起作用

module sample(clk, w, a, b, c, o );

input clk;    
input signed [15:0] w;    
input signed [15:0] a;    
input signed [15:0] b;    
input signed [15:0] c;    
output reg signed [15:0] o;    
reg signed [15:0] temp;    
reg signed [15:0] temp1;    
reg signed [15:0] temp2;    

reg signed [15:0] c_previous;
wire signed c_zero_cross;

assign c_zero_cross = (c_previous[15] == c[15]) ? 1'b0 : 1'b1;

always @(posedge clk) begin

    c_previous <= c;

    if (w < 16'b0000101100110011) begin    
         o <= a;          
    end    
    else begin    
        if(c_zero_cross) begin
            o <= b;
        end else begin
            o <= a;
        end
    end
end    

endmodule

Answer 2

老兄，缩进它会帮助你和我们的代码; - ）

如果我理解你的问题和时钟是相同的clk信号，我建议你这样：

always @(posedge clk) begin    
    if (w<16'b0000101100110011) begin    
        temp <= a;    
        big  <= 0; //flag
    end    
    else begin    
        big <= 1; //flag
    end
end    

always @ (posedge c or negedge c) begin
    if (big == 1) begin
        temp <= b;
    end
end

当您将verilog逻辑编写为C程序逻辑时似乎。你应该这样做。您需要尝试思考硬件如何构建您的电线。这是你手上的平行权力; - ）

关于=和＆lt; =的经验法则。如果你总是在@（posedge / negedge）块中，请使用＆lt; =。但请检查http://www.asic-world.com/tidbits/blocking.html以更好地理解它。

Verilog中的周期延迟

2 个答案: