我的设备树存在问题，尤其是“generic-uio”。
我有这个设备树（它指的是Zynq 7020）：
/ {
compatible = "xlnx,zynq-7000";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&gic>;
aliases {
ethernet0 = ð
serial0 = &uart1;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
ps7_cortexa9_0: cpu@0 {
bus-handle = <&axi>;
clock-latency = <1000>;
clocks = <&clkc 3>;
compatible = "arm,cortex-a9";
device_type = "cpu";
interrupt-handle = <&gic>;
operating-points = <666667 1000000 333334 1000000 222223 1000000>;
reg = <0x0>;
};
ps7_cortexa9_1: cpu@1 {
bus-handle = <&axi>;
clocks = <&clkc 3>;
compatible = "arm,cortex-a9";
device_type = "cpu";
interrupt-handle = <&gic>;
reg = <0x1>;
};
};
pmu {
compatible = "arm,cortex-a9-pmu";
interrupts = <0 5 4>, <0 6 4>;
interrupt-parent = <&gic>;
reg = <0xf8891000 0x1000>, <0xf8893000 0x1000>;
reg-names = "cpu0", "cpu1";
};
axi: amba@0 {
compatible = "simple-bus";
#address-cells = <0x1>;
#size-cells = <0x1>;
ranges;
gic: intc@f8f01000 {
interrupt-controller;
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
reg = <0xf8f01000 0x1000>,
<0xf8f00100 0x0100>;
};
pl310@f8f02000 {
compatible = "arm,pl310-cache";
cache-unified;
cache-level = <2>;
reg = <0xf8f02000 0x1000>;
arm,data-latency = <3 2 2>;
arm,tag-latency = <2 2 2>;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
status = "disabled";
reg = <0xe0000000 0x1000>;
interrupts = <0 27 4>;
interrupt-parent = <&gic>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 23>, <&clkc 40>;
port-number = <0>;
current-speed = <115200>;
device_type = "serial";
};
uart1: uart@e0001000 {
compatible = "xlnx,xuartps";
reg = <0xe0001000 0x1000>;
interrupts = < 0 50 4>;
interrupt-parent = <&gic>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 24>, <&clkc 41>;
port-number = <0>;
current-speed = <115200>;
device_type = "serial";
};
ps7_dma: ps7-dma@f8003000 {
#dma-cells = <1>;
#dma-channels = <8>;
#dma-requests = <4>;
compatible = "arm,primecell", "arm,pl330";
interrupt-parent = <&gic>;
interrupts = <0 13 4 0 14 4 0 15 4 0 16 4 0 17 4 0 40 4 0 41 4 0 42 4 0 43 4>;
reg = <0xf8003000 0x1000>;
clocks = <&clkc 27>;
clock-names = "apb_pclk";
};
/******* SEE HERE - SLCR *******/
slcr: slcr@f8000000 {
#address-cells = <1>;
#size-cells = <1>;
//generic-uio has been added
compatible = "generic-uio", "xlnx,zynq-slcr","syscon";
reg = <0xf8000000 0x1000>;
ranges;
clkc: clkc {
#clock-cells = <1>;
clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", "cpu_3or2x",
"cpu_2x", "cpu_1x", "ddr2x", "ddr3x", "dci",
"lqspi", "smc", "pcap", "gem0", "gem1",
"fclk0", "fclk1", "fclk2", "fclk3", "can0",
"can1", "sdio0", "sdio1", "uart0", "uart1",
"spi0", "spi1", "dma", "usb0_aper", "usb1_aper",
"gem0_aper", "gem1_aper", "sdio0_aper", "sdio1_aper", "spi0_aper",
"spi1_aper", "can0_aper", "can1_aper", "i2c0_aper", "i2c1_aper",
"uart0_aper", "uart1_aper", "gpio_aper", "lqspi_aper", "smc_aper",
"swdt", "dbg_trc", "dbg_apb";
compatible = "xlnx,ps7-clkc";
ps-clk-frequency = <33333333>;
fclk-enable = <0xf>;
reg = <0x100 0x100>;
};
};
timer@0xf8001000 {
compatible = "cdns,ttc";
reg = <0xf8001000 0x1000>;
interrupts = < 0 10 4 0 11 4 0 12 4 >;
interrupt-parent = <&gic>;
clocks = <&clkc 6>;
};
timer@f8f00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0xf8f00600 0x20>;
interrupts = <1 13 0x301>;
clocks = <&clkc 4>;
interrupt-parent = <&gic>;
};
swdt@f8005000 {
device_type = "watchdog";
compatible = "xlnx,ps7-wdt-1.00.a", "xlnx,zynq-wdt-1.00.a";
reg = <0xf8005000 0x100>;
interrupts = <0 9 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 45>;
reset = <0>;
timeout = <10>;
};
scuwdt@f8f00620 {
device_type = "watchdog";
compatible = "arm,mpcore_wdt";
reg = <0xf8f00620 0x20>;
clocks = <&clkc 4>;
reset = <1>;
};
eth: eth@e000b000 {
compatible = "xlnx,ps7-ethernet-1.00.a";
reg = <0xe000b000 0x1000>;
interrupts = <0 22 4>;
interrupt-parent = <&gic>;
#address-cells = <0x1>;
#size-cells = <0x0>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 13>, <&clkc 30>;
xlnx,enet-clk-freq-hz = <0x17d7840>;
xlnx,enet-reset = "MIO 11";
xlnx,enet-slcr-1000mbps-div0 = <0x8>;
xlnx,enet-slcr-1000mbps-div1 = <0x1>;
xlnx,enet-slcr-100mbps-div0 = <0x8>;
xlnx,enet-slcr-100mbps-div1 = <0x5>;
xlnx,enet-slcr-10mbps-div0 = <0x8>;
xlnx,enet-slcr-10mbps-div1 = <0x32>;
xlnx,eth-mode = <0x1>;
xlnx,has-mdio = <0x1>;
xlnx,ptp-enet-clock = <111111115>;
};
gpio: gpio@e000a000 {
compatible = "xlnx,ps7-gpio-1.00.a", "xlnx,zynq-gpio-1.00.a", "xlnx,zynq-gpio-1.0";
reg = <0xe000a000 0x1000>;
interrupts = <0 20 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 42>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
sdhci@e0100000 {
compatible = "xlnx,ps7-sdio-1.00.a", "arasan,sdhci-8.9a";
reg = <0xe0100000 0x1000>;
interrupts = <0 24 4>;
interrupt-parent = <&gic>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clkc 21>, <&clkc 32>;
xlnx,has-cd = <0x1>;
clock-frequency = <50000000>;
};
usb: usb@e0002000 {
compatible = "xlnx,ps7-usb-1.00.a", "xlnx,zynq-usb-1.00.a";
reg = <0xe0002000 0x1000>;
interrupts = <0 21 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 28>;
dr_mode = "host";
phy_type = "ulpi";
};
spi0: spi@e0006000 {
compatible = "cdns,spi-r1p6", "xlnx,zynq-spi-1.00.a", "xlnx,ps7-spi-1.00.a";
interrupt-parent = <&gic>;
interrupts = <0 26 4>;
clock-names = "ref_clk", "aper_clk", "pclk";
clocks = <&clkc 25>, <&clkc 34>, <&clkc 34>;
num-chip-select = <4>;
reg = <0xe0006000 0x1000>;
speed-hz = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi1: spi@e0007000 {
compatible = "cdns,spi-r1p6", "xlnx,zynq-spi-1.00.a", "xlnx,ps7-spi-1.00.a";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
clock-names = "ref_clk", "aper_clk", "pclk";
clocks = <&clkc 26>, <&clkc 35>, <&clkc 35>;
num-chip-select = <4>;
reg = <0xe0007000 0x1000>;
speed-hz = <100000000>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
qspi0: qspi@e000d000 {
#address-cells = <1>;
#size-cells = <0>;
bus-num = <0>;
compatible = "xlnx,zynq-qspi-1.00.a", "xlnx,ps7-qspi-1.00.a";
interrupt-parent = <&gic>;
interrupts = <0 19 4>;
clock-names = "ref_clk", "aper_clk";
clocks = <&clkc 10>, <&clkc 43>;
is-dual = <0>;
num-chip-select = <1>;
reg = <0xe000d000 0x1000>;
xlnx,fb-clk = <0x1>;
xlnx,qspi-clk-freq-hz = <0xbebc200>;
xlnx,qspi-mode = <0x0>;
primary_flash: ps7-qspi@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p80";
reg = <0x0>;
spi-max-frequency = <50000000>;
partition@0x00000000 {
label = "boot";
reg = <0x00000000 0x00500000>;
};
partition@0x00500000 {
label = "bootenv";
reg = <0x00500000 0x00020000>;
};
partition@0x00520000 {
label = "config";
reg = <0x00520000 0x00020000>;
};
partition@0x00540000 {
label = "image";
reg = <0x00540000 0x00a80000>;
};
partition@0x00fc0000 {
label = "spare";
reg = <0x00fc0000 0x00000000>;
};
};
};
devcfg@f8007000 {
compatible = "xlnx,zynq-devcfg-1.0";
reg = <0xf8007000 0x100>;
interrupts = <0 8 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>;
clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3";
};
xadc@f8007100 {
compatible = "xlnx,zynq-xadc-1.00.a", "xlnx,ps7-xadc-1.00.a";
reg = <0xf8007100 0x20>;
interrupts = <0 7 4>;
interrupt-parent = <&gic>;
clocks = <&clkc 12>;
};
ps7_ddrc_0: ps7-ddrc@f8006000 {
compatible = "xlnx,ps7-ddrc-1.00.a", "xlnx,ps7-ddrc", "xlnx,zynq-ddrc-1.0";
reg = <0xf8006000 0x1000>;
xlnx,has-ecc = <0x0>;
} ;
ps7_ocm_0: ps7-ocm@f800c000 {
compatible = "xlnx,ps7-ocmc-1.00.a", "xlnx,zynq-ocmc-1.0";
interrupt-parent = <&gic>;
interrupts = <0 3 4>;
reg = <0xf800c000 0x1000>;
};
};
};
我需要在C用户空间驱动程序（在Android下运行）下访问SLCR寄存器，并且由于Android不允许打开/ dev / mem用于安全目的，我“mmap”通过generic-uio注册（所以我将打开/dev/uioX然后调用mmap）。
但是内核不会将SLCR“分配”为generic-uio，因为我没有在/dev/uio or /sys/class/uio/下看到它（我只看到UIOx被分配给成功映射的其他外设）。
我认为这是与空“ranges”属性相关的问题，但如果我写“ranges = <0 0 0xf8000000 0x1000>;”之类的内容，我认为没有任何变化。
有人可以给我一个提示吗？
P.S。 我正在使用C用户空间驱动程序，因为我想重用为Linux应用程序编写的大部分代码。