Question

我一直在努力，下面是我的代码。我无法弄清楚为什么计数器没有将其输出传递给fulladder。

entity main is
    port(   
                clock: in std_logic;                                        --clock
                WE: IN std_logic;                                          --write enable
                WA: IN std_logic_vector(1 DOWNTO 0);                --write address
                RAE: IN std_logic;                                      --read enable ports A & B
                RAA: IN std_logic_vector(1 DOWNTO 0);           --read address port A & B
                --PortA: OUT std_logic_vector(7 DOWNTO 0);        --output port A & B
                --Clock: IN STD_LOGIC;
                Number: in std_logic_vector(0 to 7);
                --Clock: in std_logic;
                --Load: in std_logic;
                Reset: in std_logic;        -- counter output
             --A : in STD_LOGIC_VECTOR (7 downto 0);
             --B : in STD_LOGIC_VECTOR (7 downto 0);
                --sum : out STD_LOGIC_VECTOR (7 downto 0);
               Cout : out STD_LOGIC;
                X: in std_logic_vector(7 downto 0);
                Y: in std_logic_vector(7 downto 0);
                xeqy: out std_logic;
                D: IN std_logic_vector(7 DOWNTO 0) := ;                 --input
                --E: IN std_logic;
                --D: IN std_logic_vector(7 DOWNTO 0);
                OUTPUT: out std_logic_vector(7 DOWNTO 0)
        );
end main;

architecture Behavioral of main is

        component counter is
            Port(
                 Number: in std_logic_vector(0 to 7);
                Clock: in std_logic;
                --Load: in std_logic;
                Reset: in std_logic;
                Output: out std_logic_vector(0 to 7) );
        end component;

        component comp_8bit is
            port(
                X: in std_logic_vector(7 downto 0);
                Y: in std_logic_vector(7 downto 0) := "00000000";               
                xeqy, xlty, xgty: out std_logic
            );
        end component;



        component fullAdder is
            Port(
                 A : in STD_LOGIC_VECTOR (7 downto 0);
                 B : in STD_LOGIC_VECTOR (7 downto 0);
                 sum : out STD_LOGIC_VECTOR (7 downto 0);
                 Cout : out STD_LOGIC);
        end component;

        component regfile port
        (
                clock: IN std_logic;                       --clock
                WE: IN std_logic;                          --write enable
                WA: IN std_logic_vector(1 DOWNTO 0);       --write address
                D: IN std_logic_vector(7 DOWNTO 0);        --input
                RAE: IN std_logic;                               --read enable ports A 
                RAA: IN std_logic_vector(1 DOWNTO 0);        --read address port A 
                PortA: OUT std_logic_vector(7 DOWNTO 0)    --output port A 
        );
        end component;

        component TriStateBuffer port
        (
            E: IN std_logic;
            D: IN std_logic_vector(7 DOWNTO 0);
            OUTPUT: OUT std_logic_vector(7 DOWNTO 0)
        );
        end component;

        signal n: std_logic_vector(7 downto 0);
        signal l: std_logic_vector(7 downto 0);
        signal o: STD_LOGIC_VECTOR(7 downto 0);
        signal m,t: std_logic_vector(7 downto 0);


    begin

                U1 : Counter port map (Number, Clock, Reset,m);
                t <= m;
                U2 : comp_8bit port map (t, Y, xeqy);
                U4 : regfile port map (clock, WE, WA, n, RAE, RAA, l );
                U3 : fullAdder port map (l, t, n, Cout );

                U5 : TriStateBuffer port map (E, l,OUTPUT);
                Output <= t;
end Behavioral;

Answer 1

一些观察结果：

这种组件实例化很难调试。你应该远离那个。坚持使用更常用的 PORT_NAME =＆gt;信号; 接近
代码甚至不应该编译。例如，在TriStateBuffer实例化中，信号E输入甚至不存在于主实体中。
计数器的输出确实连接到FullAdder的输入，因为您具有 t＆lt; = m; 分配。我只是不明白为什么你没有直接在FullAdder的输入中使用m
代码是图片的近似值。但它仍然缺少一些诸如加载输入之类的东西。

请澄清。

虽然这本身不是答案，但由于我还没有足够的声誉，我无法发表评论。

vhdl中的专用数据路径，用于下图

1 个答案: