Question

有人可以解释一下为什么我对下面的模拟有一个时钟延迟以及如何解决它，它不应该是因为我在输出上缺少一点......

entity outBit is
port(   clk1 : in STD_LOGIC; 
        clk2 : in STD_LOGIC;
      -- reset  : in STD_LOGIC;
        int_in : in INTEGER;
        bit_out : out STD_LOGIC); --_VECTOR of 32
end outBit ;

我的实体和 clk 1 的每个上升沿都是一个整数。根据它是什么整数（1,2,3,4 ......），它选择数组的相应行。该行是32位。我想输出每个 clk2 的32位中的一位。例如，如果 clk1 = 100 ，则 clk2 = 100/32 。

architecture Behavioral of outBit is
signal temp : array; --the array is fixed
signal output_bits : std_logic_vector(31 downto 0);
signal bit_i : integer := 31; --outputting a single bit out of 32 each time
begin

    temp(0) <= "11111111111111111111111111111111";
    temp(1) <= "11111111111111111111111111111110";
    temp(2) <= "11111111111111111111111111111100";
    -- etc 

output_bits <= temp(int_in);

    process(clk2)
      --outputting a single bit out of 32 each time
      --variable bit_i : integer := 31; 
      begin
        if rising_edge(clk2) then
          bit_out <= output_bits(bit_i);
          if bit_i = 0 then
            bit_i <= 31;
          else
            bit_i <= bit_i - 1;
          end if;
        end if;
      end process;
end Behavioral;

不需要的延迟如下所示。我想每32个周期读取新行（根据输入整数）等等....

顺便说一下，第一时钟（代码中），（图中的第二个时钟）并不是真的相对于问题只是为了得到整数来的想法

Answer 1

如果你想摆脱bit_out延迟，不要把它变成触发器：

library ieee;                      -- add missing context clause
use ieee.std_logic_1164.all;

entity outbit is
    port (
    --    clk1:       in  std_logic;  -- not relevant
        clk2:       in  std_logic;
     -- reset:      in  std_logic;
        int_in:     in  integer;
        bit_out:    out std_logic  --_vector of 32
    );
end entity outbit;

architecture behavioral of outbit is
    type bit_array is array (0 to 3) of std_logic_vector(0 to 31); -- added
    signal temp : bit_array; --the array is fixed -- non_reserved word name
    signal output_bits : std_logic_vector(31 downto 0);
    subtype index_int is  integer range 0 to 31;  -- changed bit_i type 
    signal bit_i: index_int := 31; --outputting a single bit out of 32 each time

begin

    temp(0) <= "11111111111111111111111111111111";
    temp(1) <= "11111111111111111111111111111110";
    temp(2) <= "11111111111111111111111111111100";
    temp(3) <= "11011001110000110101001000101110"; -- added
    -- etc 

    output_bits <= temp(int_in);

    process(clk2)
      --outputting a single bit out of 32 each time
      --variable bit_i : integer := 31; 
      begin
        if rising_edge(clk2) then
         --  bit_out <= output_bits(bit_i);   -- moved
          if bit_i = 0 then
            bit_i <= 31;
          else
            bit_i <= bit_i - 1;
          end if;
        end if;
      end process;

      bit_out <= output_bits(bit_i);           -- moved to here

end architecture behavioral;

将bit_out赋值移出时钟条件if语句。（它可以是并发信号分配，代表32：1多路复用器）。

添加测试平台以完成Minimal, Complete, and Verifiable example：

library ieee;
use ieee.std_logic_1164.all;

entity outbit_tb is
end entity;

architecture foo of outbit_tb is
    signal clk2:    std_logic := '1';
    subtype temp_index is integer  range 0 to 3;
    signal int_in:  temp_index := 3;
    signal bit_out: std_logic;
begin
CLOCK:
    process
    begin
        wait for 5 ns;  -- so can multiply clocks in my head to get stop time
        clk2 <= not clk2;
        if now > 360 ns then
            wait;
        end if;
    end process;
DUT:
    entity work.outbit
        port map (
            clk2 => clk2,
            int_in => int_in,
            bit_out => bit_out
        );
end architecture;

延迟消失了：

不需要的一个时钟延迟vhdl

1 个答案: