Question

如果我使用getChildren，我不会在前端对类别进行排序，如果我使用getChildren那么它不会像在admin中那样对类别进行排序，但如果我使用getChildrenCategories则没有结果

  <?php

$cats = Mage::getModel('catalog/category')->load(74)->getChildren();

$catIds = explode(',',$cats);

$categories = array();
foreach($catIds as $catId) {
     $category = Mage::getModel('catalog/category')->load($catId);



    $categories[$category->getName()] = array(
        'url' => $category->getUrl(),
        'img' => $category->getImageUrl()
    );
}

ksort($categories, SORT_STRING);
?>
<ul>
    <?php foreach($categories as $name => $data): ?>
        <li>
            <a href="<?php echo $data['url']; ?>" title="<?php echo $name; ?>">
                <img class="cat-image" src="<?php echo $data['img']; ?>" />
            </a>
        </li>
    <?php endforeach; ?>
</ul>

Answer 1

使用有序集合。见下面的例子：

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity I2CBus is
    PORT(
        SYSCLK_N : IN    STD_LOGIC;     --system 200MHz differential clock
        SYSCLK_P : IN    STD_LOGIC;
        BTN      : IN    STD_LOGIC;     -- to manually change reset

        SCL      : INOUT STD_LOGIC;     --SCL & SDA lines
        SDA      : INOUT STD_LOGIC;
        SCL_cpy  : OUT   STD_LOGIC;     --SCL & SDA lines
        SDA_cpy  : OUT   STD_LOGIC
    );
end I2CBus;
architecture Behavioral of I2CBus is
    component IIC_Master is
        Generic(input_clock : integer;  --system clock
                bus_clock   : integer);
        Port(CLOCK   : in    STD_LOGIC;
             RESET_N : in    STD_LOGIC; --Active low
             ENA     : in    STD_LOGIC; --Enable active high
             ADR     : in    STD_LOGIC_VECTOR(6 downto 0); --target address
             RW      : in    STD_LOGIC; --read low, write high
             REG     : in    STD_LOGIC_VECTOR(7 downto 0); --target register
             DAT_WR  : in    STD_LOGIC_VECTOR(7 downto 0); --data to write to slave
             DAT_RD  : out   STD_LOGIC_VECTOR(7 downto 0); --data to read from slave
             BUSY    : out   STD_LOGIC; --high when busy
             SCL     : inout STD_LOGIC; --serial clock of i2C bus
             SDA     : inout STD_LOGIC; --serial data on bus
             ACK_ERR : buffer STD_LOGIC); --flag if wrong ack from slave
    end component;
    component DCM
        port(
            SYSCLK_P : in  std_logic;   -- Clock in ports 200MHz differential
            SYSCLK_N : in  std_logic;
            -- Clock out ports
            SYSCLK   : out std_logic    --300 MHz clock out
        );
    end component;
    -----Clock signals -------------
    signal sysclk      : std_logic;     --300 mhz system clock
    ----Internal Signals------------
    signal ack_err     : std_logic;     --error from dvi slave
    signal busy        : std_logic;     --is I2C master busy?
    signal slave_dout  : std_logic_vector(7 downto 0); --data out from slave
    signal reset_n     : std_logic;     --reset low
    signal i2c_wr      : STD_LOGIC;     --R/W value to send
    signal i2c_wdata   : STD_LOGIC_VECTOR(7 downto 0); --data to send
    signal i2c_regdata : STD_LOGIC_VECTOR(7 downto 0); --target register
begin
    --------Instantiate DCM------------------
    DCM_Clks : DCM
        port map(                       -- Clock in ports
            SYSCLK_P => SYSCLK_P,       --Map input clocks directly
            SYSCLK_N => SYSCLK_N,
            -- Clock out ports
            SYSCLK   => SYSCLK);
    ------------------------------------------
    ---Instantiate I2C Bus Driver-------------
    I2C_Master : IIC_Master
        Generic map(input_clock => 300000000, --system clock
                    bus_clock   => 300000000 / 16)
        Port map(CLOCK   => sysclk,     --300 MHz system clock (runs at 1/8th that)
                 RESET_N => RESET_N,    --get reset from dvi initialiser
                 ENA     => '1',        --enable signal from above
                 ADR     => "1010110",  --target DVI address straight from input
                 RW      => i2c_wr,     --get R/W from initialiser 
                 DAT_WR  => i2c_wdata,  --data to write from initialiser
                 REG     => i2c_regdata, -- target register
                 DAT_RD  => open,       --data read from DVI device (inactive at present)
                 BUSY    => busy,       --I2C finished writing
                 SCL     => SCL,        -- output straight to SCL
                 SDA     => SDA,        -- output straight to SDA
                 ACK_ERR => ack_err);   --flag if wrong ack from slave
    --------------------------------------------
    reset_proc : process(sysclk)
        variable counter : integer range 0 to 4;
        variable edge    : boolean; --used to detect busy falling edge
    begin
        if rising_edge(sysclk) then
            if busy = '1' then
                edge := true; --next '0' will be an edge
            end if;
            if busy = '0' and edge and counter < 3 then
                counter := counter + 1; --increment counter
                edge    := false; --reset edge
            end if;
            case counter is
                when 0 =>
                    i2c_wr      <= '0'; --set to write
                    i2c_regdata <= x"AA"; --send new target register
                    i2c_wdata   <= x"99"; --send new write data
                when 1 =>
                    i2c_regdata <= x"FF";
                    i2c_wdata   <= x"55";
                when 2 =>
                    i2c_regdata <= x"BB";
                    i2c_wdata   <= x"77"; --WARNING occurs here when sending x"77"
                when others => null;
            end case;
        end if;
    end process;
    reset_n <= not BTN;                 --reset process;
    SDA_cpy <= SDA;                     --copy SDA & SCL to observable pins
    SCL_cpy <= SCL;
end Behavioral;

然后，您可以遍历集合以呈现项目。

getChildrenCategories不在magento中工作，在admin中按位置排序

1 个答案: