Question

展位乘数代码为： -

module ni(prod, a, b, busy, mc, mp, clk, start);
output [15:0] prod;
output [7:0] a, b;
output busy;
input [7:0] mc, mp;
input clk, start;
reg [7:0] A, Q, M;
reg Q_1;
reg [3:0] count;
wire [7:0] sum, difference;
always @(posedge clk)
begin
if (start) begin

A <= 8'b0;
M <= mc;
Q <= mp;
Q_1 <= 1'b0;

count <= 4'b0;
end
else begin

case ({Q[0], Q_1})
         2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
         2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
         default: {A, Q, Q_1} <= {A[7], A, Q};
      endcase




count <= count + 1'b1;
end
end
alu adder (sum, A, M, 1'b0);
alu subtracter (difference, A, ~M, 1'b1);
assign prod = {A, Q};
assign a = A;
assign b = Q ;
assign busy = (count < 8);
initial 
  begin 
    $monitor($time,"prod=%b, A=%b, Q=%b, Q_1=%b, M=%d, sum=%d, difference=%d, busy==%b, mc=%b, mp=%b, clk=%b, start=%b",
                      prod, A, Q, Q_1, M, sum,difference, busy, mc, mp, clk, start);
  end
endmodule
//The following is an alu.
//It is an adder, but capable of subtraction:
//Recall that subtraction means adding the two's complement--
//a - b = a + (-b) = a + (inverted b + 1)
//The 1 will be coming in as cin (carry-in)
module alu(out, a, b, cin);
output [7:0] out;
input [7:0] a;
input [7:0] b;
input cin;

assign out = a + b + cin;

endmodule

我想知道这些代码行： -

case ({Q[0], Q_1})
             2'b0_1 : {A, Q, Q_1} <= {sum[7], sum, Q};
             2'b1_0 : {A, Q, Q_1} <= {difference[7], difference, Q};
             default: {A, Q, Q_1} <= {A[7], A, Q};
          endcase

解释以下逻辑： -

乘数和被乘数放在Q和 M寄存器分别。还有一个1位寄存器逻辑上在右边 Q寄存器的最低有效位（Q0）并指定为Q-1;它的使用很快就会解释。乘法的结果将出现在A和Q中寄存器。 A和Q-1是初始化为0.如前所述，控制逻辑扫描的位一次乘以一个。现在，当检查每个位时，还检查其右侧的位。如果两位是相同（1-1或0-0），然后是A，Q和Q-1寄存器的所有位转移到右边 1位如果两个位不同，则将被乘数加到或从A中减去寄存器，取决于两位是0-1还是1-0。以下添加或减法，发生右移。无论哪种情况，都是正确的转变这是最左边的位 A，即An-1，不仅被转移到An-2，而且还留在 AN-1。这是必需的保留A和Q中数字的符号。它被称为算术移位，因为它保留了标志位。

Answer 1

实际上{}运算符组合了sum [7]，sum和Q，并按照指定的顺序将它分配给左侧变量，即A，Q，Q-1。所以A的左位保持不变。< / p>

请解释这些verilog代码？

1 个答案: