当我尝试合成以下代码时，我得到如下错误：
INTERNAL_ERROR：Xst：cmain.c：3423：1.29 - 进程将终止。对于 关于这个问题的技术支持，请用此打开WebCase 项目附在http://www.xilinx.com/support。
在调试代码时，我发现问题出在第232行（代码中的Last if循环（错误行：oup＆lt; = mul [o_addr];））。在这里我试图将输出内存块转换为串行从模块中取出。就像，如果我评论这一行，代码是可综合的。我知道错误的原因，但我不知道如何解决它。任何人都能帮助我吗？
此外，删除错误的部分，同时生成编程文件我收到以下错误：
错误：Bitgen：342 - 此设计包含具有位置的引脚 （LOC）不是用户指定的或I / O标准（IOSTANDARD） 不是用户指定的。这可能会导致I / O争用或 与电路板功率或连接不兼容的影响 性能，信号完整性或在极端情况下会造成损坏 设备或与之连接的组件。阻止 此错误，强烈建议指定所有引脚位置和
I / O标准，以避免潜在的争用或冲突和允许 适当的比特流创建。将此错误降级为警告和 允许使用未指定的I / O位置创建比特流或 标准，您可以应用以下bitgen开关：-g UnconstrainedPins：允许错误：Bitgen：157 - Bitgen将终止 因为上述错误。
module optima_6(clk,i_data,i_coeff,en,ans,oup);
parameter n_bit = 8; // number of bits of coefficients
parameter n_depth = 8; // total number of coefficients
parameter n_addr = 4; // number of bits of address
parameter n_data = 8; // number of bits on input data
parameter n_i = 26;
parameter n_j = 26;
input clk,en;
output reg [0:0] ans;
output integer oup;
input [n_data-1:0] i_data; // inpput data of length n_data
input [n_bit-1:0] i_coeff; // inpput data of length n_data
reg [1:0] count = 1; // initialize the algorithm
reg [n_addr-1:0] addr = 0; // counter and address indicator for converting all the coefficients in to odd
reg [n_addr-1:0] c1 = 0; // counter for generating required and realized sets
reg [n_addr-1:0] r_addr = 0; // counter and address indiicator inside i1 and j1 loop
reg [n_addr-1:0] s_addr = 0; // counter for storing input coefficients
reg [n_addr-1:0] o_addr = 0; // counter for output
reg [n_bit-1:0] data; // to hold the immediate coefficient in the loop
reg [n_data-1:0] i_str; // to store the input data
reg [n_bit-1:0] i1 = 0 ; // i for finding the distance
reg [n_bit-1:0] j1 = 0 ; // j for finding the distance
reg [n_addr:0] c_rez = 0; // counter for findind number of realised elements
reg [n_addr:0] l_rez = 0; // length of realized coefficients
reg [0:0] flag_1 = 0; // indication of the complition of realizing coefficients by using only 1
//reg [0:0] ans; // flag for indicating the answer
reg [n_bit-1:0] coeff1 = 0; // temporary storage for elements of realised set
reg [n_bit-1:0] coeff2 = 0 ; // temporary storage for elements of realised set
reg [n_bit-1:0] rez1 = 0 ; // counter for accessing elements from realised set for coeff1
reg [n_bit-1:0] rez2 = 0 ; // counter for accessing elements from realised set for coeff2
reg [n_bit-1:0] var1 = 0;
reg [n_bit-1:0] shift [n_depth-1:0]; // set of shifts
reg [n_bit-1:0] shift1 [n_depth-1:0]; // set of shifts
reg [n_bit-1:0] coeff [n_depth-1:0]; // set of coefficients
reg [n_bit-1:0] coefff [n_depth-1:0]; // input set of coefficients
reg [n_bit-1:0] req [n_depth-1:0]; // required coefficients set
reg [n_bit-1:0] rez [n_depth:0]; // realizzed coefficients set
integer mul [n_depth-1:0]; // set of final multiplications
integer m1;
integer m2;
integer sum; // temporary storage of the addition
integer minus; // temporary storage of subtraction
always @(posedge clk) begin
if(en == 1) begin // initialize the algorithm
if(s_addr <= n_depth-1) begin
coefff[s_addr] = s_addr;
shift[s_addr] = 0;
s_addr = s_addr + 1;
i_str = i_data;
end
// convert all the even coefficients in to odd by shifting them to right. apply according operation of shifting left the coefficient.
else if (addr <= n_depth) begin
data = coefff[addr];
if(data != 0) begin
if (data[0] == 0) begin
coefff[addr] = {0,data[n_bit-1 : 1]};
mul[addr] = {i_str[n_bit-2:0],i_str[n_bit-1]};
i_str = mul[addr];
shift[addr] = shift[addr] + 1;
end
else begin
if (data[0] == 1) begin
coefff[addr] = data;
mul[addr] = i_str;
addr = addr + 1;
i_str = i_data;
end
end
end
else begin
coefff[addr] = data;
mul[addr] = 0;
addr = addr + 1;
end
end
end
end
always @(posedge clk) begin
// form required and realied sets
if(addr >= n_depth) begin
rez[0] <= 1;
if(c1 < n_depth) begin
coeff[c1] <= coefff[c1];
if(coefff[c1] == 1) begin
rez[c1+1] <= coefff[c1];
req[c1] <= 0;
c_rez <= c_rez+1;
end
else begin
rez[c1+1] <= 0;
req[c1] <= coefff[c1];
end
c1 <= c1+1;
end
end
// initialize the algorithm. Find the coefficients those are realised by 1.
if (c_rez < n_depth-1 && flag_1 == 0 && c1 == n_depth) begin
if (rez1 <= n_depth) begin
if(rez[rez1] == 0) begin
rez1 <= rez1 + 1;
end
else begin
if(rez1 == 0) begin
m1 <= i_data;
end
else begin
m1 <= mul[rez1 - 1];
end
coeff1 <= rez[rez1];
if(rez2 <= n_depth) begin
if(rez[rez2] == 0) begin
rez2 <= rez2 + 1;
end
else begin
if(rez2 == 0) begin
m2 <= i_data;
end
else begin
m2 <= mul[rez2 - 1];
end
coeff2 <= rez[rez2];
if(i1 < n_i) begin
if(j1 < n_j) begin
sum <= (coeff1 << i1)+(coeff2 << j1); // addition
minus <= ((coeff1 << i1) > (coeff2 << j1))? ((coeff1 << i1)-(coeff2 << j1)) : ((coeff2 << j1)-(coeff1 << i1)); // subtraction
if(sum[0] == 1 || minus[0] == 1 ) begin
count <= count+1;
if(r_addr <= n_depth-1 && count == 2) begin // check wether any coefficient matches either sum or minus.
case (req[r_addr])
0 : begin
end
sum : begin
mul[r_addr] <= (m1 << (shift[r_addr] + i1)) + (m2 << (shift[r_addr] + j1));
rez[r_addr+1] <= req[r_addr];
req[r_addr] <= 0;
coeff[r_addr] <= 0;
c_rez <= c_rez + 1;
end
minus : begin
mul[r_addr] <= ((m1 << (shift[r_addr] + i1)) > (m2 << (shift[r_addr] + j1))) ? ((m1 << (shift[r_addr] + i1)) - (m2 << (shift[r_addr] + j1))) : ((m2 << (shift[r_addr] + j1)) - (m1 << (shift[r_addr] + i1)));
rez[r_addr+1] <= coeff[r_addr];
req[r_addr] <= 0;
coeff[r_addr] <= 0;
c_rez <= c_rez+1;
end
default : begin
req[r_addr] <= coeff[r_addr];
rez[r_addr+1] <= 0;
end
endcase
r_addr <= r_addr + 1;
if (r_addr == n_depth-1) begin
j1 <= j1+1;
r_addr <= 0;
end
count <= 1;
end // end of r_addr loop
end
else begin
j1 <= j1+1;
r_addr <= 0;
if (j1 == n_j-1) begin
i1 <= i1+1;
j1 <= 0;
end
end
if (j1 == n_j-1 && r_addr == n_depth-1 && count == 2) begin
i1 <= i1+1;
j1 <= 0;
end
end //end of j1 loop
if (i1 == n_i-1 && j1 == n_j-1) begin
rez2 <= rez2 + 1;
i1 <= 0;
end
end // end of i1 loop
end
end // end of rez2 loop
if(rez2 == n_depth) begin
rez2 <= rez1 + 1;
rez1 <= rez1 + 1;
end
end
end // end of rez1 loop
if((rez1 == n_depth) && (rez2 == n_depth)) begin
if(c_rez != l_rez) begin
rez1 <= 0;
rez2 <= 0;
i1 <= 0;
j1 <= 0;
l_rez <= c_rez;
end
else begin
flag_1 <= 1;
end
end
end
if (c_rez == n_depth-1) begin
ans <= 1;
if(o_addr <= n_depth) begin
**oup <= mul[o_addr];** // <=== error
o_addr <= o_addr + 1;
end
end
end
endmodule