加载设计时出错

Question

我试图在测试版中添加一个mif文件而我正在收到错误

这里我使用的是modelsim模拟器，我收到了错误无意义的参考文献端口＆＃39; dout＆＃39;的非法输出或输入端口连接。

加载设计时出错

    `timescale 1ns / 1ps

    module ESC_tb;


    // Internal TB Signal Definition 
    reg clock; 
    reg reset;
     wire [4:0] pc_out; 
     wire [7:0] acc_out; 
     wire [7:0] mdr_out; 
     // DUT Instantiation 
     ESC instESC(.clock (clock), 
                    .reset (reset),
                    .pc_out (pc_out),
                    .acc_out(acc_out), 
                    .mdr_out(mdr_out)
                    ); 
    // Initialize block for Clock and Reset 
    initial 
    begin : RESET 

        reset = 0; 
        #7 reset = 1; 
        #18 reset = 0; 

    end 

    initial 
    begin : CLOCK 

        clock = 1; 
        #5 clock = 0; 
        forever #(5) clock = ~clock; 

    end

    // Loading Program and Data Memory 
    initial 
    begin : MEMLOAD 
        #5; 
 **// GETTING ERROR AT THIS POINT**     
      $readmemh("program.mif", memory);

/ 66 /

$display("Loaded Memory with program.mif file"); 
    end 

    initial 
    begin : DUMP_FINISH 
        $dumpvars; 
        #1000 
        $finish(2); 
    end 
    endmodule

MEMORY.FILE

module memory (clock, addr, din, we, dout,clear);
// Input/Output Declaration
    input clock;
    input [4:0] addr;
    input [7:0] din;
    input we,clear;
    output [7:0] dout;

    // Signal Type Definition
    wire clock;
    wire [4:0] addr;
    wire [7:0] din;
    wire we;
    wire [7:0] dout;// Memory Array Declaration of Size 16x256
    reg [7:0] mem [0:31];
// Memory Write Operation
always @(posedge clock) 
begin
    if(we)
    mem[addr] <= din;
    if(clear)
    mem[addr] <= 0;

end
// Memory Read Operation

assign dout = mem[addr];
// End of Module Declaration


endmodule

Answer 1

memory是一个模块，$readmemh正在寻找一个数组。您需要提供从测试平台到mem（在memory模块中）的完整路径，或在$readmemh模块中调用memory。

来自TB：$readmemh("program.mif", ESC_tb.instESC./*rest of path*/.mem);
来自memory模块：initial $readmemh("program.mif", mem);

未解决的对“记忆”的引用＆＃39;

加载设计时出错

1 个答案: