Question

如何组合/捆绑语句以供进一步使用和更好地处理？例如，一些像这样的任务将在未来的例程调用中多次使用。

{trigger: 'selection'}

进入类似的事情。

ADDR_PC     <= "0000000000";
ADDR_OP_A   <= "00000";
ADDR_OP_B   <= "00000";             
OP_CODE     <= OP_NOP;  
OP_IMMED    <= IMMED_NULL;
WE_SREG     <= "00000"; -- S V N C Z

我不知道VHDL是否有可能做到这一点。任何提示都会有所帮助。

Answer 1

记录和/或汇总：

library ieee;
use ieee.std_logic_1164.all;

entity op_decoded is
end entity;

architecture foo of op_decoded is
    -- These declarations probably want to be in a package
    constant IMMED_NULL:    std_logic_vector (8 downto 0) := (others => '0');
    constant OP_NOP:        std_logic_vector (5 downto 0) := (others => '0');

    type decode_op is 
        record 
            PC:         std_logic_vector (7 downto 0);
            OP_A:       std_logic_vector (4 downto 0);
            OP_B:       std_logic_vector (4 downto 0);
            OP_CODE:    std_logic_vector (5 downto 0);
            OP_IMMED:   std_logic_vector (8 downto 0);
            WE_SREG:    std_logic_vector (4 downto 0);  -- S V N C Z
        end record;

        constant NOP:  decode_op :=  (
                PC => "00000000", 
                OP_A => "00000", 
                OP_B => "00000",
                OP_CODE => OP_NOP,
                OP_IMMED => IMMED_NULL,
                WE_SREG => "00000"
            );
    -- actual signals
    signal ADDR_PC:    std_logic_vector (7 downto 0);
    signal ADDR_OP_A:  std_logic_vector (4 downto 0);
    signal ADDR_OP_B:  std_logic_vector (4 downto 0);
    signal OP_CODE:    std_logic_vector (5 downto 0);
    signal OP_IMMED:   std_logic_vector (8 downto 0);
    signal WE_SREG:    std_logic_vector (4 downto 0);

    signal pipe1:       decode_op;
    signal pipe_disc:   decode_op;

begin
    (ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= NOP;

    pipe1 <= NOP;

    pipe_disc <= (pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
                  pipe1.OP_IMMED, pipe1.WE_SREG);

end architecture;

分析，阐述和模拟（显示它的语法和语义正确）。

还有一个聚合目标，右侧聚合（提供类型）：

     (ADDR_PC, ADDR_OP_A, ADDR_OP_B, OP_CODE, OP_IMMED, WE_SREG) <= 
     decode_op'(pipe1.PC, pipe1.OP_A, pipe1.OP_B, pipe1.OP_CODE,
                pipe1.OP_IMMED, pipe1.WE_SREG);

Answer 2

VHDL有记录（C称它为struct）。

声明示例：

type T_MY_RECORD is record
  Member1  : STD_LOGIC;
  Member2  : STD_LOGIC_VECTOR(15 downto 0);
end record;

signal mySignal1  : T_MY_RECORD;
signal mySignal2  : T_MY_RECORD;

用法示例：

mySignal1  <= (
  Member1 => '1',
  Member2 => x"12FC"
);
mySignal2.Member1 <= '0';

记录可以嵌套，例如为了旗帜。

Answer 3

记录和/或聚合是一种可能性，但另一种方法是在驱动信号的过程中声明一个过程，然后调用该过程，如：

process (clk_i) is
  procedure NOP is
  begin
    ADDR_PC     <= "0000000000";
    ADDR_OP_A   <= "00000";
    ADDR_OP_B   <= "00000";
    OP_CODE     <= OP_NOP;
    OP_IMMED    <= IMMED_NULL;
    WE_SREG     <= "00000"; -- S V N C Z
  end procedure;
begin
  if rising_edge(clk_i) then
    ...
    NOP;
    ...
  end if;
end process;

这适用于模拟和可综合代码。

VHDL中的Bundle语句

3 个答案: