我一直在收到这个令人讨厌的错误,即没有声明std_logic。我不知道为什么我收到此错误,因为我已经包含了所有必要的库。 这是我的代码和错误。
--------------------------------------------------------------------- -------------
-- Company:
-- Engineer:
--
-- Create Date: 15:26:41 08/23/2015
-- Design Name:
-- Module Name: Deficit-Round_Robbin_algorithem - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
package TwoDArray is
Type array_integer is array(1 to 6) of integer range 0 to 6;
end package TwoDArray;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity Deficit_Round_Robbin_algorithem is
generic(
Quantom:integer range 0 to 256:=2;
Num_queues:integer:=5 ;
IN_FIFO_DEPTH_BIT:integer:=6
);
port(
clk,axi_resetn,m_axis_tready:in std_logic;
--packet_size:in array_integer range 0 to Num_queues+1;
--fifo_out_tlast,empty:in std_logic_vector(Num_queues - 1 downto 0);
--depth_of_fifo:in integer range 0 to Num_queues+1;
--rd_en:out std_logic_vector(Num_queues - 1 downto 0);
pkt_fwd:out std_logic
);
end Deficit_Round_Robbin_algorithem;
architecture Behavioral of Deficit_Round_Robbin_algorithem is
--signal cur_queue,cur_queue_next,cur_queue_plus1:integer range 0 to Num_queues-1:=0;
--signal pkt_fwd_next:std_logic:='0';
--
--signal Drr_counter:array_integer ;
--
--subType STATE_TYPE is bit_vector (1 downto 0);
--signal next_state,state:STATE_TYPE :="00"; --00 start state
--constant Idle:STATE_TYPE:="00";
--constant WR_PKT:STATE_TYPE:="01";
begin
--cur_queue_plus1<=0 when cur_queue=Num_queues-1 else cur_queue + 1;
--Drr_counter[cur_queue]<=Drr_counter[cur_queue] + Quantom;
--Medvedev_state_diagram:process(state,cur_queue,empty,m_axis_tready,fifo_out_tlast,depth_of_fifo) is
--begin
-- cur_queue_next <= cur_queue;
-- rd_en <= (others =>'0');
-- pkt_fwd_next <= '0';
-- case state is
-- when Idle=> if(empty[cur_queue]='0') then
-- if(m_axis_tready) then
-- if(Drr_counter[cur_queue] >= packet_size[cur_queue]) then
-- next_state<= WR_PKT;
-- rd_en[cur_queue] <= '1';
-- pkt_fwd_next <= '1';
-- end if;
-- end if;
-- else
-- cur_queue_next <= cur_queue_plus1;
-- end if;
-- end case;
--end process;
end Behavioral;
我的错误
ERROR:HDLCompiler:69 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 42: <std_logic> is not declared.
ERROR:HDLCompiler:69 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 47: <std_logic> is not declared.
ERROR:HDLCompiler:854 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 34: Unit <deficit_round_robbin_algorithem> ignored due to previous errors.
ERROR:HDLCompiler:374 - "I:\xilinx\Deficit-Round_Rrobbin\Deficit-Round_Robbin_algorithem.vhd" Line 51: Entity <deficit_round_robbin_algorithem> is not yet compiled.
答案 0 :(得分:4)
使用子句(库声明)实际上是VHDL中库单元声明(包,实体,配置等)的一部分。它们不全局应用于文件中声明的所有库单元。
因此,在您的情况下,用于导入文件顶部的IEEE库的use子句仅应用于包TwoDArray
。在软件包声明后,您需要重新定义适用于Deficit_Round_Robbin_algorithem
的库。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
package TwoDArray is
Type array_integer is array(1 to 6) of integer range 0 to 6;
end package TwoDArray;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library work;
use work.TwoDArray.all;
entity Deficit_Round_Robbin_algorithem is
generic(
...
编辑:根据评论为实体的使用条款添加了TwoDArray
包。